A Technique for Improving the Precision of the Direct Measurement of Junction Temperature in Power Light-Emitting Diodes

Extending the lifetime of power light-emitting diodes (LEDs) is achievable if proper control methods are implemented to reduce the side effects of an excessive junction temperature, TJ. The accuracy of state-of-the-art LED junction temperature monitoring techniques is negatively affected by several factors, such as the use of external sensors, calibration procedures, devices aging, and technological diversity among samples with the same part number. Here, a novel method is proposed, indeed based on the well-known technique consisting in tracking the LED forward voltage drop when a fixed forward current is imposed but exploiting the voltage variation with respect to room temperature. This method, which limits the effects of sample heterogeneity, is applied to a set of ten commercial devices. The method led to an effective reduction of the measurement error, which was below 1 °C.

Design, Fabrication and Characterization of 10kV/100A 4H-SiC PiN Power Rectifier

A 10kV/100A SiC PiN rectifier with MRM-JTE (multiple-ring modulated junction termination extension) is designed, fabricated and characterized. The optimized MRM-JTE achieves high breakdown capability and extends the optimal JTE dose window. A 100μm thick epitaxial SiC PiN rectifier with a doping concentration of 5×1014cm−3 has been fabricated using a standard TZ-JTE process. A 5.4V forward voltage drop is obtained at 100A forward current. Moreover, a measured breakdown voltage is up to 13.5kV corresponding to about 96% of the ideal parallel plane junction. The fabricated device exhibits a low RON,SP of 3.76mΩ·cm2 at 200A/cm2 , and a high BFOM of 48.5GW/cm2. In addition, the C-V characteristic and reverse recovery switch characteristic are also analyzed. In this paper, the successfully fabrication of high-voltage SiC PiN rectifier provides a further development for high-voltage high-power SiC power modules.

Investigation of Electrical Contacts to p-Grid in SiC Power Devices Based on Charge Storage Effect and Dynamic Degradation

P-grid is a typical feature in power devices to block high off-state voltage. In power devices, the p-grid is routinely coupled to an external electrode with an Ohmic contact, but Schottky contact to the p-grid is also proposed/adopted for certain purposes. This work investigates the role of contact to p-grid in power devices based on the commonly adopted technology computer-aided design (TCAD) device simulations, with the silicon carbide (SiC) junction barrier Schottky (JBS) diode as a case study. The static characteristics of the JBS diode is independent of the nature of the contact to p-grid, including the forward voltage drop (VF) and the breakdown voltage (BV). However, during the switching process, a Schottky contact would cause storage of negative charges in the p-grid, which leads to an increased VF during switching operation. On the contrary, an Ohmic contact provides an effective discharging path for the stored negative charges in the p-grid, which eliminates the dynamic degradation issues. Therefore, the necessity of an Ohmic contact to p-grid in power devices is clarified.

Wide-Range Prediction of Ultra-High Voltage SiC IGBT Static Performance Using Calibrated TCAD Model

In this paper, a technology computer-aided design (TCAD) model of a silicon carbide (SiC) insulated-gate bipolar transistor (IGBT) has been calibrated against previously reported experimental data. The calibrated TCAD model has been used to predict the static performance of theoretical SiC IGBTs with ultra-high blocking voltage capabilities in the range of 20-50 kV. The simulation results of transfer characteristics, IC-VGE, forward characteristics, IC-VCE, and blocking voltage characteristics are studied. The threshold voltage is approximately 5 V, and the forward voltage drop is ranging from VF = 4.2-10.0 V at IC = 20 A, using a charge carrier lifetime of τA = 20 μs. Furthermore, the forward voltage drop impact for different process dependent parameters (i.e., carrier lifetimes, mobility/scattering and trap related defects) and junction temperature are investigated in a parametric sensitivity analysis. The wide-range simulation results may be used as an input to facilitate high power converter design and evaluation. In this case, the TCAD simulated static characteristics of SiC IGBTs is compared to silicon (Si) IGBTs in a modular multilevel converter in a general high-power application. The results indicate several benefits and lower conduction energy losses using ultra-high voltage SiC IGBTs compared to Si IGBTs.

1.2 kV, 10 A, 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Low On-State Voltage Drop

Bidirectional power switches are used in matrix-or cyclo-converters and in multistage inverter circuits to facilitate high-frequency AC-to-AC conversion. A new 1.2 kV bidirectional MOSFET (BiDFET) with low on-resistance is achieved and demonstrated using two discrete SiC power MOSFET bare die chips, packaged within a four-terminal custom-designed module. Static and dynamic characterization has been carried out to inspect the on-state and switching behaviour of the BiDFET. The BiDFET is shown to have a low forward voltage drop of 0.6 V at a current of 10 A, which is more than 2.5x smaller than previous Si IGBT and SiC MOSFET based bidirectional switch implementations.

Mobility Models Based on Forward Current-Voltage Characteristics of P-type Pseudo-Vertical Diamond Schottky Barrier Diodes

Compared with silicon and silicon carbide, diamond has superior material parameters and is therefore suitable for power switching devices. Numerical simulation is important for predicting the electric characteristics of diamond devices before fabrication. Here, we present numerical simulations of p-type diamond pseudo-vertical Schottky barrier diodes using various mobility models. The constant mobility model, based on the parameter μconst, fixed the hole mobility absolutely. The analytic mobility model resulted in temperature- and doping concentration-dependent mobility. An improved model, the Lombard concentration, voltage, and temperature (CVT) mobility model, considered electric field-dependent mobility in addition to temperature and doping concentration. The forward voltage drop at 100 A/cm2 using the analytic and Lombard CVT mobility models was 2.86 and 5.17 V at 300 K, respectively. Finally, we used an empirical mobility model based on experimental results from the literature. We also compared the forward voltage drop and breakdown voltage of the devices, according to variations in p- drift layer thickness and cathode length. The device successfully achieved a low specific on-resistance of 6.8 mΩ∙cm2, a high breakdown voltage of 1190 V, and a high figure-of-merit of 210 MW/cm2.

Gate Current and Snapback of 4H-SiC Thyristors on N+ Substrate for Power-Switching Applications

High-power switching applications, such as thyristor valves in a high-voltage direct current converter, can use 4H-SiC. The numerical simulation of the 4H-SiC devices requires specialized models and parameters. Here, we present a numerical simulation of the 4H-SiC thyristor on an N+ substrate gate current during the turn-on process. The base-emitter current of the PNP bipolar junction transistor (BJT) flow by adjusting the gate potential. This current eventually activated a regenerative action of the thyristor. The increase of the gate current from P+ anode to N+ gate also decreased the snapback voltage and forward voltage drop (Vf). When the doping concentration of the P-drift region increased, Vf decreased due to the reduced resistance of a low P-drift doping. An increase in the P buffer doping concentration increased Vf owing to enhanced recombination at the base of the NPN BJT. There is a tradeoff between the breakdown voltage and forward characteristics. The breakdown voltage is increased with a decrease in concentration, and an increase in drift layer thickness occurs due to the extended depletion region and reduced peak electric field.

Forward Voltage Drop Induced by an Abnormal Threading Dislocation Aggregation in 4H-SiC GTO Devices

An abnormal star-like defect was found on the failed SiC gate turn-off thyristor (GTO) devices after metal removal and KOH etching at 450 °C in this work. It is of extraordinary larger size of 210–580 µm, even much larger than the etch pit of a micropipe in 4H-SiC. In addition, the abnormal star-like defect, exhibiting the consistent orientation with the six-fold symmetry of silicon carbide, was found to consist of several penetrating dislocations with the help of a LEXT OLS4000 3D laser confocal microscope. These abnormal star-like etch pits can severely reduce the forward blocking characteristic of GTOs, while exerting insignificant influence on the forward current-voltage characteristics between anode and gate electrode of the 4H-SiC GTO devices. Interestingly, the relationship between forward voltage drop and dislocation density is affected by the abnormal star-like defect. A regular increase of forward voltage drop at 100 A/cm2 was observed with the increasing dislocation density, while this correlation disappears in the presence of an abnormal star-like defect.

10 kV Silicon Carbide PiN Diodes—From Design to Packaged Component Characterization

This paper presents the design, fabrication and characterization results obtained on the last generation (third run) of SiC 10 kV PiN diodes from SuperGrid Institute. In forward bias, the 59 mm2 diodes were tested up to 100 A. These devices withstand voltages up to 12 kV on wafer (before dicing, packaging) and show a low forward voltage drop at 80 A. The influence of the temperature from 25 °C to 125 °C has been assessed and shows that resistivity modulation occurs in the whole temperature range. Leakage current at 3 kV increases with temperature, while being three orders of magnitude lower than those of equivalent Si diodes. Double-pulse switching tests reveal the 10 kV SiC PiN diode’s outstanding performance. Turn-on dV/dt and di/dt are −32 V/ns and 311 A/µs, respectively, whereas turn-off dV/dt and di/dt are 474 V/ns and −4.2 A/ns.

Simulation Study for the Structural Cell Design Optimization of 15kV SiC p-Channel IGBTs

In this paper, the structural cell design optimization of 15kV 4H-SiC p-channel IGBT is performed. The effects of the parameters of JFET region on the blocking voltage and the forward characteristics are analyzed by numerical simulations. The results indicate that the JFET width and JFET region concentration have an important effect on the performance of IGBTs. Based on the simulation structure in this paper, the optimum JFET width is 10μm, and the optimum JFET concentration is 7×1015cm−3. Meanwhile, they should be carefully designed to achieve the best trade-off between the blocking voltage and the forward voltage drop.