High Vth enhancement mode GaN power devices with high ID, max using hybrid ferroelectric charge trap gate stack

2017 ◽  
Author(s):  
C. H. Wu ◽  
S. C. Liu ◽  
C. K. Huang ◽  
Y. C. Chiu ◽  
P. C. Han ◽  
...  
Keyword(s):  
Power Devices ◽  
Gate Stack ◽  
Charge Trap ◽  
Enhancement Mode

E-Mode GaN MIS-HEMT Using Ferroelectric Charge Trap Gate Stack with Low Dynamic On-Resistance and High Vth Stability by Field Plate Engineering

2021 ◽  
pp. 1-1
Author(s):  
Jui-Sheng Wu ◽  
Chih-Chieh Lee ◽  
Chia-Hsun Wu ◽  
Min-Lu Kao ◽  
You-Chen Weng ◽  
...  
Keyword(s):  
Gate Stack ◽  
Charge Trap ◽  
Field Plate

scholarly journals Design and Analysis of High Mobility Enhancement-Mode 4H-SiC MOSFETs Using a Thin-SiO2/Al2O3 Gate-Stack

2019 ◽  
Vol 66 (4) ◽  
pp. 1710-1716 ◽  
Author(s):  
J. Urresti ◽  
F. Arith ◽  
S. Olsen ◽  
N. Wright ◽  
A. O'Neill
Keyword(s):  
High Mobility ◽  
Gate Stack ◽  
Enhancement Mode

A Charge Storage Based Enhancement Mode AlGaN/GaN High Electron Mobility Transistor

2018 ◽  
Vol 913 ◽  
pp. 870-875 ◽  
Author(s):  
Hui Wang ◽  
Ling Li Jiang ◽  
Ning Wang ◽  
Hong Yu Yu ◽  
Xin Peng Lin
Keyword(s):  
Electron Mobility ◽  
Gate Dielectric ◽  
High Electron Mobility Transistor ◽  
Charge Storage ◽  
High Electron ◽  
High Electron Mobility ◽  
Charge Trap ◽  
Enhancement Mode ◽  
A Charge ◽  
The Impact

In this work, a charge storage based enhancement mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT) is proposed and studied. A stacked gate dielectrics, consisting of a tunnel oxide, a charge trap layer and a blocking oxide are applied in the HEMT structure. The E-mode can be realized by negative charge storage within the charge trap layer during the programming process. The impact of the programming condition and the thickness of the dielectrics on the threshold voltage (Vth) are simulated systematically. It is found that the Vth increases with the increasing programming voltage and time due to the increase of the storage charge. Under proper programming condition, the Vth can be increased to more than 2 V. Moreover, It is also found that the Vth increases with the decrease of the thickness of the dielectrics. In addition, it is found that the breakdown voltage of such HEMT can be adjusted by varying the gate dielectric stacks.

Degradation mechanism of Schottky P-GaN gate stack in GaN power devices under neutron irradiation

2021 ◽  
Vol 119 (13) ◽  
pp. 133503
Author(s):  
Ruize Sun ◽  
Xinghuan Chen ◽  
Chao Liu ◽  
Wanjun Chen ◽  
Bo Zhang
Keyword(s):  
Neutron Irradiation ◽  
Degradation Mechanism ◽  
Power Devices ◽  
Gate Stack

High-Performance Normally-OFF GaN MIS-HEMTs Using Hybrid Ferroelectric Charge Trap Gate Stack (FEG-HEMT) for Power Device Applications

2018 ◽  
Vol 39 (7) ◽  
pp. 991-994 ◽  
Author(s):  
Chia-Hsun Wu ◽  
Ping-Cheng Han ◽  
Shih-Chien Liu ◽  
Ting-En Hsieh ◽  
Franky Juanda Lumbantoruan ◽  
...  
Keyword(s):  
High Performance ◽  
Power Device ◽  
Gate Stack ◽  
Charge Trap ◽  
Device Applications

Fabrication of Self-Aligned Enhancement-Mode $ \hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ MOSFETs With $ \hbox{TaN/HfO}_{2}\hbox{/AlN}$ Gate Stack

2008 ◽  
Vol 29 (6) ◽  
pp. 557-560 ◽  
Author(s):  
D. Shahrjerdi ◽  
T. Rotter ◽  
G. Balakrishnan ◽  
D. Huffaker ◽  
E. Tutuc ◽  
...  
Keyword(s):  
Gate Stack ◽  
Enhancement Mode

Analysis of fluorine effects on charge-trap flash memory of W/TiN/Al2O3/Si3N4/SiO2/poly-Si gate stack

2020 ◽  
Vol 164 ◽  
pp. 107713 ◽  
Author(s):  
Tae Yoon Lee ◽  
Seung Hwan Lee ◽  
Jun Woo Son ◽  
Sang Jae Lee ◽  
Jae Hoon Bong ◽  
...  
Keyword(s):  
Flash Memory ◽  
Gate Stack ◽  
Charge Trap

Ionizing Dose-Tolerant Enhancement-Mode Cascode for High-Voltage Power Devices

2017 ◽  
Vol 64 (1) ◽  
pp. 382-387
Author(s):  
A. F. Witulski ◽  
A. L. Sternberg ◽  
J. D. Rowe ◽  
R. D. Schrimpf ◽  
J. Zydel ◽  
...  
Keyword(s):  
High Voltage ◽  
Power Devices ◽  
Enhancement Mode

scholarly journals Charge trap layer enabled positive tunable Vfb in β-Ga2O3 gate stacks for enhancement mode transistors

2020 ◽  
Vol 117 (17) ◽  
pp. 172101
Author(s):  
Dipankar Biswas ◽  
Chandan Joishi ◽  
Jayeeta Biswas ◽  
Prabhans Tiwari ◽  
Saurabh Lodha
Keyword(s):  
Gate Stacks ◽  
Charge Trap ◽  
Enhancement Mode
Sign in / Sign up

Export Citation Format

Share Document