scholarly journals Charge trap layer enabled positive tunable Vfb in β-Ga2O3 gate stacks for enhancement mode transistors

2020 ◽  
Vol 117 (17) ◽  
pp. 172101
Author(s):  
Dipankar Biswas ◽  
Chandan Joishi ◽  
Jayeeta Biswas ◽  
Prabhans Tiwari ◽  
Saurabh Lodha
Keyword(s):  
Gate Stacks ◽  
Charge Trap ◽  
Enhancement Mode

A Charge Storage Based Enhancement Mode AlGaN/GaN High Electron Mobility Transistor

2018 ◽  
Vol 913 ◽  
pp. 870-875 ◽  
Author(s):  
Hui Wang ◽  
Ling Li Jiang ◽  
Ning Wang ◽  
Hong Yu Yu ◽  
Xin Peng Lin
Keyword(s):  
Electron Mobility ◽  
Gate Dielectric ◽  
High Electron Mobility Transistor ◽  
Charge Storage ◽  
High Electron ◽  
High Electron Mobility ◽  
Charge Trap ◽  
Enhancement Mode ◽  
A Charge ◽  
The Impact

In this work, a charge storage based enhancement mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT) is proposed and studied. A stacked gate dielectrics, consisting of a tunnel oxide, a charge trap layer and a blocking oxide are applied in the HEMT structure. The E-mode can be realized by negative charge storage within the charge trap layer during the programming process. The impact of the programming condition and the thickness of the dielectrics on the threshold voltage (Vth) are simulated systematically. It is found that the Vth increases with the increasing programming voltage and time due to the increase of the storage charge. Under proper programming condition, the Vth can be increased to more than 2 V. Moreover, It is also found that the Vth increases with the decrease of the thickness of the dielectrics. In addition, it is found that the breakdown voltage of such HEMT can be adjusted by varying the gate dielectric stacks.

Non-Visible Defect Analysis of OTP Device

2011 ◽  
Author(s):  
C.Q. Chen ◽  
G.B. Ang ◽  
Z.X. Xing ◽  
Y.N. Hua ◽  
Z.Q. Mo ◽  
...  
Keyword(s):  
Trap Center ◽  
Data Retention ◽  
Auger Analysis ◽  
Cross Sectional ◽  
Critical Dimensions ◽  
Charge Trap ◽  
Root Cause ◽  
Transmission Electron ◽  
Electrical Analysis ◽  
Visible Defect

Abstract Several product lots were found to suffer from data retention failures in OTP (one time program) devices. PFA (physical failure analysis) was performed on these devices, but nothing abnormal was observed. Cross-sectional TEM (transmission electron microscopy) revealed no physical defects or abnormal CDs (critical dimensions). In order to isolate the failed layer or location, electrical analysis was conducted. Several electrical simulation experiments, designed to test the data retention properties of OTP devices, were preformed. Meilke's method [1] was also used to differentiate between mobile ion contamination and charge trap centers. Besides Meilke's method, a new electrical analysis method was used to verify the analysis results. The results of our analysis suggests that SiN charge trap centers are the root cause for the data retention failures, and the ratio of Si/N is the key to charge trap center formation. Auger analysis was used to physically check the Si/N ratio of OTP devices. The results support our hypothesis. Subsequent DOE (Design Of Experiment) experiments also confirm our analysis results. Key Words: OTP, data retention, Non-visible defect, AFP, charge trap center, mobile ion.

High-current recessed gate enhancement-mode ultrawide bandgap Al x Ga1−x N channel MOSHFET with drain current 0.48 A mm−1 and threshold voltage +3.6 V

2021 ◽  
Vol 14 (1) ◽  
pp. 014003
Author(s):  
Shahab Mollah ◽  
Kamal Hussain ◽  
Abdullah Mamun ◽  
Mikhail Gaevski ◽  
Grigory Simin ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
High Current ◽  
Enhancement Mode ◽  
Recessed Gate

Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device

2021 ◽  
pp. 1-13
Author(s):  
Jong-Moon Choi ◽  
Do-Wan Kwon ◽  
Je-Joong Woo ◽  
Eun-Je Park ◽  
Kee-Won Kwon
Keyword(s):  
Neural Network ◽  
Linear Charge ◽  
Charge Trap ◽  
On Chip

scholarly journals Investigation of Re-program Scheme in Charge Trap Based 3D NAND Flash Memory

2021 ◽  
pp. 1-1
Author(s):  
Ting Cheng ◽  
Jianquan Jia ◽  
Lei Jin ◽  
Xinlei Jia ◽  
Shiyu Xia ◽  
...  
Keyword(s):  
Flash Memory ◽  
Program Scheme ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Charge Trap

scholarly journals Gate Capacitance and Off-State Characteristics of E-Mode p-GaN Gate AlGaN/GaN High-Electron-Mobility Transistors After Gate Stress Bias

2021 ◽  
Author(s):  
Yu-Chen Lai ◽  
Yi-Nan Zhong ◽  
Ming-Yan Tsai ◽  
Yue-Ming Hsin
Keyword(s):  
Leakage Current ◽  
Electron Mobility ◽  
High Electron Mobility Transistors ◽  
High Electron ◽  
High Electron Mobility ◽  
Gate Capacitance ◽  
Enhancement Mode ◽  
Electron Mobility Transistors ◽  
Higher Power ◽  
State Capacitance

AbstractThis study investigated the gate capacitance and off-state characteristics of 650-V enhancement-mode p-GaN gate AlGaN/GaN high-electron-mobility transistors after various degrees of gate stress bias. A significant change was observed in the on-state capacitance when the gate stress bias was greater than 6 V. The corresponding threshold voltage exhibited a positive shift at low gate stress and a negative shift when the gate stress was greater than 6 V, which agreed with the shift observation from the I–V measurement. Moreover, the off-state leakage current increased significantly after the gate stress exceeded 6 V during the off-state characterization although the devices could be biased up to 1000 V without breakdown. The increase in the off-state leakage current would lead to higher power loss.

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