Characterization of the Si/SiO2 Interfere Morphology from Quantum Oscillations in Fowler-Nordheim Tunneling Currents

1993 ◽  
Author(s):  
J. C. Poler ◽  
K. K. McKay ◽  
E. A. Irene
1992 ◽  
Vol 280 ◽  
Author(s):  
J. C. Poler ◽  
K. K. McKay ◽  
E. A. Irene

ABSTRACTAs design rules shrink to conform with ULSI device dimensions, gate dielectrics for MOSFET structures are required to be scaled to even thinner proportions. Upon scaling the gate oxides below ∼60Å some properties of the device, such as interface roughness, that are negligible for thicker films become critical and must be evaluated. Microroughness at the interface of ultrathin MOS capacitors has been shown to degrade these devices.We are studying the interfacial region of ∼50Å SiO2 on Si using the quantum oscillations in Fowler-Nordheim tunneling currents. The oscillations are sensitive to the electron potential and abruptness of the film and its interfaces. In particular, inelastic scattering and/or thickness inhomogeneities in the film will reduce the amplitude of the oscillations. We are using the amplitude of the oscillations to examine the degree of microroughness at the interface that results from a pre-oxidation high temperature anneal in an inert ambient containing various amounts of H2O. Preliminary AFM imaging has shown correlations supporting our microroughness interpretation of the quantum oscillation amplitudes.


1985 ◽  
Vol 28 (7) ◽  
pp. 717-720 ◽  
Author(s):  
Y. Nissan-Cohen ◽  
J. Shappir ◽  
D. Frohman-Bentchkowsky

1999 ◽  
Vol 85 (9) ◽  
pp. 6912-6916 ◽  
Author(s):  
Kouji Fujimaru ◽  
Ryouta Sasajima ◽  
Hideki Matsumura

1992 ◽  
Vol 284 ◽  
Author(s):  
D. J. Dumin ◽  
J. R. Maddux ◽  
D.-P. Wong

ABSTRACTIt has been observed that the low-level, pre-tunneling currents through thin gate oxides increased after the oxides had been stressed at high voltages. The number of traps inside of the oxide generated by the stress has been shown to increase as the 1/3 power of the fluence that had passed through the oxide during the stress. The increases in the low-level, pre-tunneling currents have been shown to be proportional to the number of stress generated traps in the oxide and not to the fluence during the stress. The voltage dependences of the excess low-level leakage currents were stress and measurement polarity dependent. Attempts have been made to fit the voltage dependences of the excess low-level currents to Fowler-Nordheim tunneling, Frenkel-Poole conduction or Schottky barrier lowering. The increase in the portion of the low-level, pre-tunneling current that was not dependent on stress/measurement polarity sequence was best fit using Schottky emission currents. The model that has been developed to describe the increases in the low-level currents has centered on trap-assisted currents through the oxides.


1999 ◽  
Vol 567 ◽  
Author(s):  
S. Okhonin ◽  
A. Ils ◽  
D. Bouvet ◽  
P. Fazan ◽  
G. Guegan ◽  
...  

ABSTRACTThe conduction band and valence band electron tunneling currents in ultra-thin SiO2 films at the transition from direct to Fowler-Nordheim tunneling regimes are studied. The slopes of the current voltage characteristics agree well with the simulations performed. The Stress-Induced Leakage Current (SILC) behavior is quite similar for both conduction and valence band currents even if the amplitude of the valence band SILC is much lower. We show that a linear dependence exists between the stress-induced interface trap density and both valence and conduction band SILC. A new model of SILC is also proposed.


2014 ◽  
Vol 2014 ◽  
pp. 1-7
Author(s):  
Enrique J. Tinajero-Perez ◽  
Jesus Ezequiel Molinar-Solis ◽  
Rodolfo Z. Garcia-Lozano ◽  
Pedro Rosales-Quintero ◽  
Jose M. Rocha-Perez ◽  
...  

The experimental results of the Fowler-Nordheim characterization using poly1-poly2 capacitors on CMOS ON Semi 0.5 μm technology are presented. This characterization allows the development, design, and characterization of a new current-mode analog nonvolatile memory. Experimental results of the memory cell architecture are presented and demonstrate the usefulness of the proposed architecture.


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