Solid Phase Epitaxy process integration on 50-nm PMOS devices: Effects of defects on chemical and electrical characteristics of ultra shallow junctions

2004 ◽  
Vol 810 ◽  
Author(s):  
R. El Farhane ◽  
C. Laviron ◽  
F. Cristiano ◽  
N. Cherkashin ◽  
P. Morin ◽  
...  
Keyword(s):  
Process Integration ◽  
Solid Phase ◽  
Cmos Process ◽  
Solid Phase Epitaxy ◽  
Electrical Characteristics ◽  
Use Of Self ◽  
Thermal Budget ◽  
Shallow Junctions ◽  
Ultra Shallow Junctions ◽  
Low Thermal Budget

ABSTRACTWe demonstrate in this paper the viability of an ultra-low thermal budget CMOS process enabling the formation of ultra shallow junctions with competitive transistor characteristics. In particular, we demonstrate in this work the influence of defects on chemical and electrical results. It is shown that the use of self-amorphizing implantation with BF2for Source/Drain, reduces the junction leakage by two decades.

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

2006 ◽  
Vol 53 (7) ◽  
pp. 1657-1668 ◽  
Author(s):  
L.-A. Ragnarsson ◽  
S. Severi ◽  
L. Trojman ◽  
K.D. Johnson ◽  
D.P. Brunco ◽  
...  
Keyword(s):  
Solid Phase ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
Low Thermal Budget

Electrical Characterization of Ultra-Shallow Junctions Formed by Diffusion From a CoSi2 Diffusion Source

1996 ◽  
Vol 427 ◽  
Author(s):  
F. La Via ◽  
E. Rimini
Keyword(s):  
Electrical Characterization ◽  
Junction Depth ◽  
Thermal Budget ◽  
Shallow Junctions ◽  
Different Temperatures ◽  
Diffusion Source ◽  
Ultra Shallow Junctions ◽  
20 Nm ◽  
Low Thermal Budget

AbstractUltra-Shallow p+/n and n+/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800÷900 °C). A thin layer (50 nm) of CoSi2 was implanted with As and BF2 and subsequently diffused at different temperatures and times to form two Ultra-Shallow junctions with a junction depth of 14 and 20 nm. These diodes were extensively investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. TEM delineation was used to controll the junction uniformity.

Leakage optimization of ultra-shallow junctions formed by solid phase epitaxial regrowth

2004 ◽  
Vol 22 (1) ◽  
pp. 306 ◽  
Author(s):  
R. Lindsay ◽  
K. Henson ◽  
W. Vandervorst ◽  
K. Maex ◽  
B. J. Pawlak ◽  
...  
Keyword(s):  
Solid Phase ◽  
Epitaxial Regrowth ◽  
Shallow Junctions ◽  
Ultra Shallow Junctions
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