Formation of silicided, ultra-shallow junctions using low thermal budget processing

1990 ◽  
Vol 19 (1) ◽  
pp. 67-88 ◽  
Author(s):  
C. M. Osburn
Keyword(s):  
Thermal Budget ◽  
Shallow Junctions ◽  
Ultra Shallow Junctions ◽  
Low Thermal Budget

Electrical Characterization of Ultra-Shallow Junctions Formed by Diffusion From a CoSi2 Diffusion Source

1996 ◽  
Vol 427 ◽  
Author(s):  
F. La Via ◽  
E. Rimini
Keyword(s):  
Electrical Characterization ◽  
Junction Depth ◽  
Thermal Budget ◽  
Shallow Junctions ◽  
Different Temperatures ◽  
Diffusion Source ◽  
Ultra Shallow Junctions ◽  
20 Nm ◽  
Low Thermal Budget

AbstractUltra-Shallow p+/n and n+/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800÷900 °C). A thin layer (50 nm) of CoSi2 was implanted with As and BF2 and subsequently diffused at different temperatures and times to form two Ultra-Shallow junctions with a junction depth of 14 and 20 nm. These diodes were extensively investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. TEM delineation was used to controll the junction uniformity.

Solid Phase Epitaxy process integration on 50-nm PMOS devices: Effects of defects on chemical and electrical characteristics of ultra shallow junctions

2004 ◽  
Vol 810 ◽  
Author(s):  
R. El Farhane ◽  
C. Laviron ◽  
F. Cristiano ◽  
N. Cherkashin ◽  
P. Morin ◽  
...  
Keyword(s):  
Process Integration ◽  
Solid Phase ◽  
Cmos Process ◽  
Solid Phase Epitaxy ◽  
Electrical Characteristics ◽  
Use Of Self ◽  
Thermal Budget ◽  
Shallow Junctions ◽  
Ultra Shallow Junctions ◽  
Low Thermal Budget

ABSTRACTWe demonstrate in this paper the viability of an ultra-low thermal budget CMOS process enabling the formation of ultra shallow junctions with competitive transistor characteristics. In particular, we demonstrate in this work the influence of defects on chemical and electrical results. It is shown that the use of self-amorphizing implantation with BF2for Source/Drain, reduces the junction leakage by two decades.

Shallow junctions in silicon via low thermal budget processing

2006 ◽  
Author(s):  
B.J. Sealy ◽  
A.J. Smith ◽  
T. Alzanki ◽  
N. Bennett ◽  
L. Li ◽  
...  
Keyword(s):  
Thermal Budget ◽  
Shallow Junctions ◽  
Low Thermal Budget

Shallow junctions in silicon via low thermal budget processing

2006 ◽  
Author(s):  
B.J. Sealy ◽  
A.J. Smith ◽  
T. Alzanki ◽  
N. Bennett ◽  
L. Li ◽  
...  
Keyword(s):  
Thermal Budget ◽  
Shallow Junctions ◽  
Low Thermal Budget

Low Thermal Budget NiSi Films on SiGe Alloys

2002 ◽  
Vol 745 ◽  
Author(s):  
S. K. Ray ◽  
T. N. Adam ◽  
G. S. Kar ◽  
C. P. Swann ◽  
J. Kolodzey
Keyword(s):  
Photoelectron Spectroscopy ◽  
Thermal Budget ◽  
X Ray ◽  
Force Microscopy ◽  
Atomic Force ◽  
Higher Temperature ◽  
Ultra Shallow Junctions ◽  
The Stability ◽  
Xps Study ◽  
Low Thermal Budget

ABSTRACTNickel silicides were formed on Si (100) substrates and CVD grown Si0.9Ge0.1/Si layers by low thermal budget annealing of evaporated Ni films to evaluate their utility for ultra shallow junctions. The phase formation and microstructure of silicides formed using conventional furnace and rapid thermal annealing were studied by x-ray diffraction, Rutherford backscattering (RBS), x-ray photoelectron spectroscopy (XPS) and atomic force microscopy. RBS simulations and XPS study revealed the formation of a ternary nickel germanosilicide phase for the SiGe alloy. The incorporation of Ge resulted in a higher temperature window for the stability of low-resistive monosilicide phase. Electrical properties of the grown silicides were characterized by four-probe resistivity and contact resistance measurements.

Influence of low thermal budget pre-anneals on the high temperature redistribution of low energy boron implants in silicon

2001 ◽  
Vol 669 ◽  
Author(s):  
F. Boucard ◽  
M. Schott ◽  
D. Mathiot ◽  
P. Rivallin ◽  
P. Holliger ◽  
...  
Keyword(s):  
High Temperature ◽  
Initial Point ◽  
High Dose ◽  
Thermal Budget ◽  
Enhanced Diffusion ◽  
High Temperature Anneal ◽  
Ultra Shallow Junctions ◽  
Low Thermal Budget ◽  
Temperature Plateau ◽  
Reference Samples

ABSTRACTIt is now well established that the transient enhanced diffusion (TED) of ion implanted boron in silicon limits the formation of the ultra-shallow junctions required for the extreme deep sub- micron devices. It is also known that this TED is linked to the fate (elimination and agglomeration) of ion implantation related excess self-interstitials. Thus it can be expected that the final high temperature redistribution is at least partly governed by the effective initial point defect distribution at the onset of the high temperature plateau.In this contribution we present the experimental evidence that low thermal pre-anneals, by affecting the initial self-interstitials distribution, affects boron redistribution during a subsequent high temperature anneal. Samples implanted with high dose boron at 3 keV were first annealed at 700°C for various durations. These samples, as well as reference samples without the pre-anneal, were then RTA annealed at various high temperatures around 1000°C. The resulting B profiles were measured by SIMS. It is found that the pre-annealed samples exhibits a clear reduction of the TED as compared with the reference ones.

Vacancy Engineering – An Ultra-Low Thermal Budget Method for High-Concentration 'Diffusionless' Implantation Doping

2008 ◽  
Vol 573-574 ◽  
pp. 295-304 ◽  
Author(s):  
Nicholas E.B. Cowern ◽  
Andrew J. Smith ◽  
Nicholas S. Bennett ◽  
Brian J. Sealy ◽  
Russell Gwilliam ◽  
...  
Keyword(s):  
Low Temperatures ◽  
High Performance ◽  
Silicon Films ◽  
Doping Profile ◽  
Junction Depth ◽  
High Concentration ◽  
Thermal Budget ◽  
Boron Implantation ◽  
Ultra Shallow Junctions ◽  
Low Thermal Budget

This paper reviews the physics and the potential application of ion-implanted vacancies for high-performance B-doped ultra-shallow junctions. By treatment of silicon films with vacancygenerating implants prior to boron implantation, electrically active boron concentrations approaching 1021 cm-3 can be achieved by Rapid Thermal Annealing at low temperatures, without the use of preamorphisation. Source/drain (S/D) junctions formed by advanced vacancy engineering implants (VEI) are activated far above solubility. Furthermore, in the case of appropriately engineered thin silicon films, this activation is stable with respect to deactivation and the doping profile is practically diffusionless. Sheet resistance Rs is predicted to stay almost constant with decreasing junction depth Xj, thus potentially outperforming other S/D engineering approaches at the ‘32 nm node’ and beyond.

Low Thermal Budget Monolithic Integration of Evanescent-Coupled Ge-on-SOI Photodetector on Si CMOS Platform

2010 ◽  
Vol 16 (1) ◽  
pp. 106-113 ◽  
Author(s):  
Kah-Wee Ang ◽  
Tsung-Yang Liow ◽  
Ming-Bin Yu ◽  
Qing Fang ◽  
Junfeng Song ◽  
...  
Keyword(s):  
Monolithic Integration ◽  
Thermal Budget ◽  
Low Thermal Budget
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