Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

2006 ◽  
Vol 53 (7) ◽  
pp. 1657-1668 ◽  
Author(s):  
L.-A. Ragnarsson ◽  
S. Severi ◽  
L. Trojman ◽  
K.D. Johnson ◽  
D.P. Brunco ◽  
...  
Keyword(s):  
Solid Phase ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
Low Thermal Budget

Solid Phase Epitaxy process integration on 50-nm PMOS devices: Effects of defects on chemical and electrical characteristics of ultra shallow junctions

2004 ◽  
Vol 810 ◽  
Author(s):  
R. El Farhane ◽  
C. Laviron ◽  
F. Cristiano ◽  
N. Cherkashin ◽  
P. Morin ◽  
...  
Keyword(s):  
Process Integration ◽  
Solid Phase ◽  
Cmos Process ◽  
Solid Phase Epitaxy ◽  
Electrical Characteristics ◽  
Use Of Self ◽  
Thermal Budget ◽  
Shallow Junctions ◽  
Ultra Shallow Junctions ◽  
Low Thermal Budget

ABSTRACTWe demonstrate in this paper the viability of an ultra-low thermal budget CMOS process enabling the formation of ultra shallow junctions with competitive transistor characteristics. In particular, we demonstrate in this work the influence of defects on chemical and electrical results. It is shown that the use of self-amorphizing implantation with BF2for Source/Drain, reduces the junction leakage by two decades.

Ni-Silicided Deep Source/Drain Junctions Formed by Solid Phase Epitaxial Regrowth

2004 ◽  
Vol 810 ◽  
Author(s):  
Anne Lauwers ◽  
Richard Lindsay ◽  
Kirklen Henson ◽  
Simone Severi ◽  
Amal Akheyar ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Solid Phase ◽  
Attractive Alternative ◽  
High Activation ◽  
Thermal Budget ◽  
Metal Gates ◽  
Epitaxial Regrowth ◽  
Deep Source ◽  
Low Thermal Budget

ABSTRACTMaking use of SPER (Solid Phase Epitaxial Regrowth) As and B deep source/drain junctions with high activation can be obtained at temperatures below 700°C. However, higher thermal budget is required to regrow and activate the dopants in the poly gates. Low junction leakage and low contact resistance can be obtained for Ni-silicided As and B SPER junctions making use of deep As and B implants. Because of the low thermal budget source/drain junctions obtained by SPER are an attractive alternative to conventional spike annealed junctions for technologies making use of metal gates.

Low thermal budget solid phase epitaxial growth of CaF2 on Si (111) substrates

1990 ◽  
Vol 19 (10) ◽  
pp. 1061-1064 ◽  
Author(s):  
R. Singh ◽  
R. P. S. Thakur ◽  
A. J. Nelson ◽  
S. C. Gebhard ◽  
A. B. Swartzlander
Keyword(s):  
Epitaxial Growth ◽  
Solid Phase ◽  
Thermal Budget ◽  
Low Thermal Budget

Metal induced crystallization of SiGe at 370°C for monolithically integrated MEMS applications

2004 ◽  
Vol 808 ◽  
Author(s):  
Sherif Sedky ◽  
Kris Baert ◽  
Chris Van Hoof ◽  
Yi Wang ◽  
Omer Van Der Biest ◽  
...  
Keyword(s):  
Strain Gradient ◽  
Microelectromechanical Systems ◽  
Solid Phase ◽  
Active Material ◽  
Mean Stress ◽  
Germanium Content ◽  
Thermal Budget ◽  
Metal Induced Crystallization ◽  
Low Thermal Budget ◽  
Induced Crystallization

Over the last decade SiGe has been proposed as a structural material for low thermal budget microelectromechanical systems (MEMS) that can be post-processed on top of standard CMOS driving and controlling electronics [1-6]. There are several ways to decrease the deposition temperature of SiGe and at the same time preserve the desired physical properties for MEMS as low electrical resistivity, high quality factor, economical growth rate and low mean stress and strain gradient. The conventional approach to reduce the crystallization thermal budget is to increase the germanium content to 60%, or more, using conventional Low Pressure Chemical Vapor Deposition (LPCVD) [1-3]. In this case highly conductive polycrystalline films can be realized, but the strain gradient is relatively high. This can be eliminated by furnace annealing at 450°C [2], which might introduce damage to the underlying circuits such as in the case of Cu/low k CMOS. This problem can be alleviated using excimer pulsed laser annealing [7, 8], which has been attractive for low thermal budget applications such as thin film transistors (TFT) [9], solar cells fabricated on glass substrates [10] and for monolithic integration of MEMS devices on top of standard driving electronics using SiGe as an active material [8, 11]. Also the use of hydrogenated microcrystalline SiGe allows for a low thermal budget [12]. In addition, metal induced crystallization has recently been proposed to enhance the crystallization of silicon at temperatures as low as 500°C, and the realized devices had outstanding performance compared to those employing conventional solid-phase crystallization [13]. This technique enhances crystallization by two methods. First, it has been observed that depositing SiGe on top of a thin Al or Ni layer, has a polycrystalline micro-structure close to the metal/ SiGe interface [11]. Annealing this film for a long period (is determined by the annealing temperature), results in metal diffusion and a subsequent crystallization of the film. Finally, when the metal is diffused completely through out the film, it can be etched away. The main disadvantage of this approach is that the mean stress is highly compressive and this might affect the functionality of surface micromachined structures [13].

A novel process for SiGe Core-Shell JAM Transistors Fabrication and thermal annealing effect on its electrical performance

2020 ◽  
Vol 1 (2) ◽  
Author(s):  
Ashish Kumar ◽  
Wen-Hsi Lee
Keyword(s):  
Process Condition ◽  
Subthreshold Swing ◽  
Electrical Performance ◽  
Core Shell ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
New Process ◽  
Comparable Performance ◽  
Higher Temperature ◽  
Film Annealing

 In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits  a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current. 

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