Dry Etching Techniques of Amorphous Silicon for Suspended Metal Membrane RF MEMS Capacitors

2002 ◽  
Vol 729 ◽  
Author(s):  
Raphaël Fritschi ◽  
Cyrille Hibert ◽  
Philippe Flückiger ◽  
Adrian M. Ionescu
Keyword(s):  
Amorphous Silicon ◽  
Rf Mems ◽  
Dry Etching ◽  
Fabrication Process ◽  
Experimental Results ◽  
Post Processing ◽  
Etching Technique ◽  
Metal Membrane ◽  
Tunable Capacitors ◽  
Wet Process

AbstractA novel dry etching technique of amorphous silicon is proposed to suspend the metal membrane of RF MEMS tunable capacitors. The proposed fabrication process is simple and excludes all the drawbacks related to a wet process. Moreover, it has the advantage of being fully compatible with CMOS post-processing. Experimental results demonstrate that the capacitor suspension beams design with meanders can reduce the tuning voltage to less than 5 to 10 V.

scholarly journals Fabrication of Graphene Nanomesh FET Terahertz Detector

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 641
Author(s):  
Yuan Zhai ◽  
Yi Xiang ◽  
Weiqing Yuan ◽  
Gang Chen ◽  
Jinliang Shi ◽  
...  
Keyword(s):  
Room Temperature ◽  
Energy Gap ◽  
Coupling Efficiency ◽  
High Sensitivity ◽  
Fabrication Process ◽  
Monolayer Graphene ◽  
Terahertz Waves ◽  
Wet Process ◽  
Graphene Nanomesh ◽  
Thz Detector

High sensitivity detection of terahertz waves can be achieved with a graphene nanomesh as grating to improve the coupling efficiency of the incident terahertz waves and using a graphene nanostructure energy gap to enhance the excitation of plasmon. Herein, the fabrication process of the FET THz detector based on the rectangular GNM (r-GNM) is designed, and the THz detector is developed, including the CVD growth and the wet-process transfer of high quality monolayer graphene films, preparation of r-GNM by electron-beam lithography and oxygen plasma etching, and the fabrication of the gate electrodes on the Si3N4 dielectric layer. The problem that the conductive metal is easy to peel off during the fabrication process of the GNM THz device is mainly discussed. The photoelectric performance of the detector was tested at room temperature. The experimental results show that the sensitivity of the detector is 2.5 A/W (@ 3 THz) at room temperature.

The Fabrication of Silicon Nanopin with CsCl Nanoislands and Dry Etching for Field Emission

2013 ◽  
Vol 562-565 ◽  
pp. 1224-1228
Author(s):  
Marina Ashmkhan ◽  
Jing Liu ◽  
Bo Wang ◽  
Fu Ting Yi
Keyword(s):  
Field Emission ◽  
Thermal Evaporation ◽  
Dry Etching ◽  
Fabrication Process ◽  
Controlled Environment ◽  
Gate Electrodes ◽  
Icp Etching ◽  
Lift Off ◽  
Photolithography Process ◽  
Ag Film

Silicon nano pin arrays with heights of 1.3-3.66um and diameter of 315-899nm, are fabricated by CsCl self-assemble for CsCl nano islands for mask and ICP etching for silicon pins. CsCl film is firstly deposited on the wafer by thermal evaporation and putted in the humid controlled environment to be developed to the CsCl islands with diameter of 341-915 nm as self-assembled technology. Then the ICP etching with SF6, CCl4, He gas is introduced to make the silicon nano pin by the mask of CsCl nano islands, and the silicon nano pins with the different height of 1.3-3.66 um are finished for field emission. The gated FEA templates are fabricated by photolithography process and the lift-off technology with Ti-Si film as the gate electrodes. The final template for field emission has the silicon nano pins with diameters of 31.7 nm on top, Ti-Ag film with thickness of 105nm and gate holes of 30um in diameter, and SU8 resist insulator structure with thickness of 4um and holes of 10um in diameter. The optimization of the fabrication process and the performance for the configuration will be made.

Interaction Between Low Temperatures Spacers and Source Drain Extensions and Pockets for Both NMOS and PMOS of the 65 nm Node Technology

2006 ◽  
Vol 912 ◽  
Author(s):  
Nathalie Cagnat ◽  
Cyrille Laviron ◽  
Daniel Mathiot ◽  
Pierre Morin ◽  
Frédéric Salvetti ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Hydrogen Content ◽  
Low Temperatures ◽  
Direct Contact ◽  
Fabrication Process ◽  
Experimental Results ◽  
The Other ◽  
Mos Transistors ◽  
Phosphorus Source ◽  
Activation Annealing

AbstractDuring the MOS transistors fabrication process, the source-drain extension areas are directly in contact with the oxide liner of the spacers stack. In previous works [1, 2, 3] it has been established that boron can diffuse from the source-drain extensions into the spacer oxide liner during the subsequent annealing steps, and that the amount of boron loss depends on the hydrogen content in the oxide, because it enhances B diffusivity in SiO2.In order to characterize and quantify the above phenomena, we performed test experiments on full sheet samples, which mimic either BF2 source-drain extensions over arsenic pockets implants, or BF2 pockets under arsenic or phosphorus source-drain extensions implants. Following the corresponding implants, the wafers were covered with different spacer stacks (oxide + nitride) deposited either by LPCVD, or PECVD. After appropriate activation annealing steps, SIMS measurements were used to characterize the profiles of the various dopants, and the corresponding dose loss was evaluated for each species.Our experimental results clearly evidence that LPCVD or PECVD spacer stacks have no influence on the arsenic profiles. On the other hand, phosphorus and boron profiles are affected. For boron profiles, each spacer type has a different influence. It is also shown that boron out-diffuses not only from the B doped source-drain extension in direct contact with the oxide layer, but also from the "buried" B pockets lying under n-doped source drain extension areas. All these results are discussed in term of the possible relevant mechanism.

RF MEMS tunable capacitors with large tuning ratio

2004 ◽  
Author(s):  
T.G.S.M. Rijks ◽  
J.T.M. van Beek ◽  
P.G. Steeneken ◽  
M.J.E. Ulenaers ◽  
J. De Coster ◽  
...  
Keyword(s):  
Rf Mems ◽  
Tunable Capacitors ◽  
Tuning Ratio

The Influence of Ambient Pressure on the Dynamic Response of RF MEMS Switches

2010 ◽  
Author(s):  
Avihay Ohana ◽  
Oren Aharon ◽  
Ronen Maimon ◽  
Boris Nepomnyashchy ◽  
Lior Kogut
Keyword(s):  
Rf Mems ◽  
Ambient Pressure ◽  
Actuation Voltage ◽  
Operating Conditions ◽  
Experimental Results ◽  
Release Time ◽  
Q Factor ◽  
Optimal Operating ◽  
Mems Switches ◽  
Rf Mems Switches

A study of the dynamic behavior of an RF MEMS switch is presented at different operating conditions. Experimental results for the actuation and release time and Q-factor as a function of the ambient pressure and actuation voltage are compared to theoretical predictions based on existing model. Optimal operating conditions (ambient pressure and actuation voltage) are determined based on two criterions: minimal actuation and release time and minimal oscillations upon switch release. In light of the experimental results optimal operating conditions determined to be 1.4Vpi at a pressure of a few torrs where actuation and release time are equal and short enough with no release oscillations. Three pressure regimes are identified with characteristic behavior of the Q-factor and actuation and release time in each regime. These behaviors have significant implications in many MEMS devices, especially RF MEMS switches.

The Submicron Fabrication Process for T Gate With a Flat Head

2018 ◽  
Author(s):  
Xiaoyu Su ◽  
Zhongjing Ren ◽  
Hao Sun ◽  
Yong Shi ◽  
Quan Pan
Keyword(s):  
Optical Microscope ◽  
Fabrication Process ◽  
Experimental Results ◽  
General Process ◽  
Gate Structure ◽  
Measurement Results

T gate structure is traditionally manufactured with a valley in its head, which requires the thickness of the head layer to thicker than the height of foot layer. As is presented in this paper, an innovative submicron fabrication process is investigated for T gate structures to construct a flat head in order to get rid of that constraint. In detail, the reason why conventional T gate fabrication cannot manufacture a flat head is analyzed, and then a general process for flat head T gate structure is proposed considering various resist and structure materials. After that, a typical submicron sample has been manufactured using aluminum and NiTi. Furthermore, the particular photo resists and recipes adopted in that sample are considered. To clearly illustrate the proposed technique as well as verify its feasibility, top views of the structure under optical microscope along with the measurement results of thickness after every step are recorded. According to those experimental results, the valley in T gate’s head is proved to be avoided during fabrication.

Patterning of silicon wafers using the plasma jet dry etching technique

Vacuum ◽  
1990 ◽  
Vol 41 (4-6) ◽  
pp. 899-901 ◽  
Author(s):  
A.M Barklund ◽  
H.-O Blom ◽  
S Berg ◽  
L Bardos
Keyword(s):  
Plasma Jet ◽  
Dry Etching ◽  
Silicon Wafers ◽  
Etching Technique

scholarly journals Amorphous silicon p-i-n diodes, deposited by the VHF-GD process: new experimental results

1996 ◽  
Vol 198-200 ◽  
pp. 1159-1162 ◽  
Author(s):  
P. Chabloz ◽  
H. Keppner ◽  
D. Fischer ◽  
D. Link ◽  
A. Shah
Keyword(s):  
Amorphous Silicon ◽  
Experimental Results
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