Gate Technology Issues for Silicon Mos Nanotransistors

1999 ◽  
Vol 584 ◽  
Author(s):  
D. M Tennant ◽  
G. L. Timp ◽  
L. E. Ocola ◽  
M. Green ◽  
T. Sorsch ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
Ring Structure ◽  
Channel Length ◽  
Low Energy ◽  
Gate Length ◽  
Direct Write ◽  
Mos Transistors ◽  
Processing Elements ◽  
Effective Channel

AbstractThis article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (∼ 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

scholarly journals Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator

2019 ◽  
Vol 8 (12S2) ◽  
pp. 61-66
Keyword(s):  
Band Gap ◽  
Mole Fraction ◽  
High Performance ◽  
Device Simulation ◽  
Channel Length ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Simulation Results ◽  
High Performance Application ◽  
Device Modelling

This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

2002 ◽  
Vol 49 (12) ◽  
pp. 2263-2270 ◽  
Author(s):  
S. Inaba ◽  
K. Okano ◽  
S. Matsuda ◽  
M. Fujiwara ◽  
A. Hokazono ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
Gate Length

Electrically Induced Junction MOSFET for High Performance Sub-50nm CMOS Technology

2002 ◽  
Vol 716 ◽  
Author(s):  
Abhisek Dixit ◽  
Rajiv O. Dusane ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Voltage ◽  
High Performance ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Channel Length ◽  
Short Channel ◽  
Channel Effects ◽  
Deep Source ◽  
Proper Scaling ◽  
Effective Channel

AbstractDegrading of short-channel effects (SCE) e.g. Drain-Induced-Barrier-Lowering (DIBL), charge-sharing etc., as CMOS devices are scaled into the sub-50nm regime, is a major roadblock for ULSI technologies. This problem can be circumvented to some extent by a proper scaling of MOSFET vertical dimensions (junction depths, oxide thickness etc.). In this work we propose a novel implementation of an electrically induced junction (EJ) MOSFET. An EJ-MOSFET is different from conventional CMOS device in that the gate voltage electrically induces the shallow source-drain extensions (SDEs). In such a device the SDEs are underneath the gate and contain low-doped regions of opposite conductivity as that of deep source-drain (S/D). In order to turn ON the device, a voltage is applied at the gate of EJ-MOSFET device, such that these low doped regions below poly-Si gate get inverted and serve as SDEs. Consequently, the effective channel length in this condition is the distance between these low-doped regions. On the contrary, at any gate voltage less than that required for inverting these regions, no SDEs are induced, and the effective channel length is equal to the physical separation between the deep S/D junctions.

New ratio method for effective channel length and threshold voltage extraction in MOS transistors

2001 ◽  
Vol 37 (11) ◽  
pp. 717 ◽  
Author(s):  
B. Cretu ◽  
T. Boutchacha ◽  
G. Ghibaudo ◽  
F. Balestra
Keyword(s):  
Threshold Voltage ◽  
Channel Length ◽  
Ratio Method ◽  
Mos Transistors ◽  
Effective Channel

Electrical and Physical Characterization of Ultrathin Silicon Oxynitride Gate Dielectric Films Formed by the Jet Vapor Deposition Technique

1999 ◽  
Vol 592 ◽  
Author(s):  
A. Karamcheti ◽  
V.H.C. Watt ◽  
T.Y. Luo ◽  
D. Brady ◽  
F. Shaapur ◽  
...  
Keyword(s):  
Secondary Ion Mass Spectrometry ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Channel Length ◽  
Silicon Oxynitride ◽  
Low Energy ◽  
Effective Dielectric Constant ◽  
Nuclear Reaction Analysis ◽  
Equivalent Thickness ◽  
Vapor Deposition Technique

ABSTRACTThis paper describes the electrical and physical characteristics of ultrathin Jet Vapor Deposited (JVD) Silicon Oxynitride films. Capacitance-Voltage measurements indicate an equivalent oxide thickness (EOT) of less than 2 nm, taking into account the quantum-mechanical correction. These films have leakage currents almost two orders of magnitude lower than thermal oxide of the same equivalent thickness. Measurements on NMOSFETs with 0.15 μm of channel length demonstrate excellent electrical properties, including high drive currents (∼0.5 mA/μm @ Vd=Vg–Vt=l.5 V), low sub-threshold swings (∼72 mV/decade), and high transconductance (∼0.36 mS/μm @ Vd=1.5 V). These films were also analyzed using a variety of physicochemical methods, including Total X-ray Fluorescence (TXRF), Atomic Force Microscopy (AFM), Nuclear Reaction Analysis (NRA), Low Energy (500 eV) Secondary Ion Mass Spectrometry (SIMS), and Transmission Electron Microscopy (TEM). Surface metal concentrations of less than 1011 atoms/cm2 were measured from the TXRF analysis. The microroughness values for these films varied between 0.15 – 0.17 nm as measured by AFM. Low energy (500 eV) SIMS and NRA indicate high [N] near the top as well as throughout the bulk of the film, and a significant amount of [O] near the top of the film. High Resolution TEM pictures show a very uniform film with a physical thickness of 2.8 ± 0.1 nM, which yields an effective dielectric constant of 5.5, consistent with these types of oxynitride films.

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