High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

2002 ◽  
Vol 49 (12) ◽  
pp. 2263-2270 ◽  
Author(s):  
S. Inaba ◽  
K. Okano ◽  
S. Matsuda ◽  
M. Fujiwara ◽  
A. Hokazono ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
Gate Length

Gate Technology Issues for Silicon Mos Nanotransistors

1999 ◽  
Vol 584 ◽  
Author(s):  
D. M Tennant ◽  
G. L. Timp ◽  
L. E. Ocola ◽  
M. Green ◽  
T. Sorsch ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
Ring Structure ◽  
Channel Length ◽  
Low Energy ◽  
Gate Length ◽  
Direct Write ◽  
Mos Transistors ◽  
Processing Elements ◽  
Effective Channel

AbstractThis article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (∼ 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals High-Performance Carbon Nanotube Field Effect Transistors with a Thin Gate Dielectric Based on a Self-Assembled Monolayer

Nano Letters ◽  
2007 ◽  
Vol 7 (1) ◽  
pp. 22-27 ◽  
Author(s):  
Ralf Thomas Weitz ◽  
Ute Zschieschang ◽  
Franz Effenberger ◽  
Hagen Klauk ◽  
Marko Burghard ◽  
...  
Keyword(s):  
Carbon Nanotube ◽  
Field Effect ◽  
High Performance ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Self Assembled Monolayer ◽  
Self Assembled

scholarly journals High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

2012 ◽  
Vol 7 (1) ◽  
pp. 431 ◽  
Author(s):  
Szu-Hung Chen ◽  
Wen-Shiang Liao ◽  
Hsin-Chia Yang ◽  
Shea-Jue Wang ◽  
Yue-Gie Liaw ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
High K ◽  
High K Gate Dielectric

scholarly journals Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator

2019 ◽  
Vol 8 (12S2) ◽  
pp. 61-66
Keyword(s):  
Band Gap ◽  
Mole Fraction ◽  
High Performance ◽  
Device Simulation ◽  
Channel Length ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Simulation Results ◽  
High Performance Application ◽  
Device Modelling

This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.

scholarly journals ALD-ZrO2 gate dielectric with suppressed interfacial oxidation for high performance MoS2 top gate MOSFETs

2020 ◽  
Author(s):  
Wen-Hsin Chang ◽  
Naoya Okada ◽  
Masayo Horikawa ◽  
Takahiko Endo ◽  
Yasumitsu Miyata ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
Interfacial Oxidation
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