Electrical and Physical Characterization of Ultrathin Silicon Oxynitride Gate Dielectric Films Formed by the Jet Vapor Deposition Technique

1999 ◽  
Vol 592 ◽  
Author(s):  
A. Karamcheti ◽  
V.H.C. Watt ◽  
T.Y. Luo ◽  
D. Brady ◽  
F. Shaapur ◽  
...  
Keyword(s):  
Secondary Ion Mass Spectrometry ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Channel Length ◽  
Silicon Oxynitride ◽  
Low Energy ◽  
Effective Dielectric Constant ◽  
Nuclear Reaction Analysis ◽  
Equivalent Thickness ◽  
Vapor Deposition Technique

ABSTRACTThis paper describes the electrical and physical characteristics of ultrathin Jet Vapor Deposited (JVD) Silicon Oxynitride films. Capacitance-Voltage measurements indicate an equivalent oxide thickness (EOT) of less than 2 nm, taking into account the quantum-mechanical correction. These films have leakage currents almost two orders of magnitude lower than thermal oxide of the same equivalent thickness. Measurements on NMOSFETs with 0.15 μm of channel length demonstrate excellent electrical properties, including high drive currents (∼0.5 mA/μm @ Vd=Vg–Vt=l.5 V), low sub-threshold swings (∼72 mV/decade), and high transconductance (∼0.36 mS/μm @ Vd=1.5 V). These films were also analyzed using a variety of physicochemical methods, including Total X-ray Fluorescence (TXRF), Atomic Force Microscopy (AFM), Nuclear Reaction Analysis (NRA), Low Energy (500 eV) Secondary Ion Mass Spectrometry (SIMS), and Transmission Electron Microscopy (TEM). Surface metal concentrations of less than 1011 atoms/cm2 were measured from the TXRF analysis. The microroughness values for these films varied between 0.15 – 0.17 nm as measured by AFM. Low energy (500 eV) SIMS and NRA indicate high [N] near the top as well as throughout the bulk of the film, and a significant amount of [O] near the top of the film. High Resolution TEM pictures show a very uniform film with a physical thickness of 2.8 ± 0.1 nM, which yields an effective dielectric constant of 5.5, consistent with these types of oxynitride films.

Future Silicon Nanocrystal Nonvolatile Memory Technology

2001 ◽  
Vol 686 ◽  
Author(s):  
Michele L. Ostraat ◽  
Jan W. De Blauwe
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Channel Length ◽  
Charge Storage ◽  
Memory Devices ◽  
Two Stage ◽  
Nanocrystal Memory

AbstractA great deal of research interest is being invested in the fabrication and characterization of nanocrystal structures as charge storage memory devices. In these flash memory devices, it is possible to measure threshold voltage shifts due to charge storage of only a few electrons per nanocrystal at room temperature. Although a variety of methods exist to fabricate nanocrystals and to incorporate them into device layers, control over the critical nanocrystal dimensions, tunnel oxide thickness, and interparticle separation and isolation remains difficult to achieve. This control is vital to produce reliable and consistent devices over large wafer areas. To address these control issues, we have developed a novel two-stage ultra clean reactor in which the Si nanocrystals are generated as single crystal, nonagglomerated, spherical aerosol particles from silane decomposition at 950°C at concentrations exceeding 108 cm−3 at sizes below 10 nm. Using existing aerosol instrumentation, it is possible to control the particle size to approximately 10% on diameter. In the second reactor, particles are passivated with a high quality oxide layer with shell thickness controllable from 0.7 to 2.0 nm. The two-stage aerosol reactor is integrated to a 200 mm wafer deposition chamber such that controlled particle densities can be deposited thermophoretically. With nanocrystal deposits of 1013 cm−2, contamination of transition metals and other elements can be controlled to less than 1010 atoms cm−2.We have fabricated 0.2 μm channel length aerosol nanocrystal floating gate memory devices using conventional MOS ULSI processing on 200 mm wafers. The aerosol nanocrystal memory devices exhibit normal transistor characteristics with drive current 30 μA/μm, subthreshold slope 200 mV/dec, and drain induced barrier lowering 100 mV/V, typical values for thick gate dielectric high substrate doped nonvolatile memory devices. Uniform Fowler-Nordheim tunneling is used to program and erase these memory devices. Despite 5 nm tunnel oxides, threshold voltage shifts > 2 V have been achieved with microsecond program and millisecond erase times at moderate operating voltages. The aerosol devices also exhibit excellent endurance cyclability with no window closure observed after 105 cycles. Furthermore, reasonable disturb times and long nonvolatility are obtained, illustrating the inherent advantage of discrete nanocrystal charge storage. No drain disturb was detected even at drain biases of 4V, indicating that little or no charge conduction occurs in the nanocrystal layer. We have demonstrated promise for aerosol nanocrystal memory devices. However, numerous issues exist for the future of nanocrystal devices. These technology issues and challenges will be discussed as directions for future work.

SIMS STUDY OF SILICON OXYNITRIDE RAPID THERMALLY GROWN IN NITRIC OXIDE

2001 ◽  
Vol 08 (05) ◽  
pp. 569-573
Author(s):  
R. LIU ◽  
K. H. KOA ◽  
A. T. S. WEE ◽  
W. H. LAI ◽  
M. F. LI ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Depth Distribution ◽  
Secondary Ion Mass Spectrometry ◽  
Gate Dielectric ◽  
State Of The Art ◽  
Rapid Thermal Processing ◽  
Growth Characteristics ◽  
Silicon Oxynitride ◽  
Mos Devices ◽  
Secondary Ion

As the gate dielectric for ULSI MOS devices scales in the ultrathin regime, it is fabricated increasingly with silicon oxynitride instead of silicon dioxide films. One way to obtain silicon oxynitride films is the rapid thermal oxidation of silicon in NO (RTNO). Earlier RTNO growth studies were not sufficiently comprehensive as well as limited by temperature uncertainty and nonuniformity across the wafer. Using a state-of-the-art rapid thermal processing (RTP) system, RTNO growth characteristics at oxidation pressures of 100 and 760 Torr, oxidation temperatures from 900 to 1200°C and oxidation times from 0 to 480 s were obtained and investigated. Anomalies in the growth characteristics were observed. It was also demonstrated that secondary ion mass spectrometry (SIMS) using the MCs + method could be used to accurately determine the depth distribution of N in ultrathin silicon oxynitride films.

Effective Dielectric Thickness Scaling for High-K Gate Dielectric Mosfets

2002 ◽  
Vol 716 ◽  
Author(s):  
Krishna Kumar Bhuwalka ◽  
Nihar R. Mohapatra ◽  
Siva G. Narendra ◽  
V Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Dielectric Thickness ◽  
High K ◽  
Fringing Field ◽  
High K Dielectric ◽  
Physical Thickness

AbstractIt has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.

scholarly journals The Effect of Nitrogen Concentration at Oxynitride Gate Insulators Formed by 28N2 + Implantation into Silicon with Additional Conventional or Rapid Thermal Oxidation

2004 ◽  
Vol 1 (2) ◽  
pp. 41-47
Author(s):  
A. G. Felício ◽  
José Alexandre Diniz ◽  
J. Godoy Fo. ◽  
I. Doi ◽  
M. A. A. Pudenzi ◽  
...  
Keyword(s):  
Thermal Oxidation ◽  
Secondary Ion Mass Spectrometry ◽  
Nitrogen Concentration ◽  
Oxide Thickness ◽  
Silicon Oxynitride ◽  
Electrical Characteristics ◽  
Mos Capacitors ◽  
Gate Insulators ◽  
Rapid Thermal Oxidation ◽  
Nitrogen Ion

Silicon oxynitride (SiOxNy) insulators have been obtained by nitrogen ion implantation into Si substrates prior to conventional or rapid thermal oxidation. These films have been used as gate insulators in nMOSFETs and MOS capacitors. nMOSFET electrical characteristics, such as field effect mobility between 390 cm2/Vs and 530 cm2/Vs, and sub-threshold slope between 70 mV/decade and 150 mV/decade, were obtained. MOS capacitors were used to obtain capacitance-voltage (C-V) and current-voltage (I-V) measurements. The Equivalent Oxide Thickness (EOT) of the films were obtained from C-V curves, resulting in values between 2.9 nm and 12 nm. SiOxNy gate insulators with EOT between 2.9 nm and 4.3 nm have presented gate leakage current densities between 3 mA/cm2 and 50 nA/cm2. The electrical characteristics were compared and correlated with the nitrogen concentration profiles at SiOxNy/Si of the structures, obtained by Secondary Ion Mass Spectrometry (SIMS).

Gate Technology Issues for Silicon Mos Nanotransistors

1999 ◽  
Vol 584 ◽  
Author(s):  
D. M Tennant ◽  
G. L. Timp ◽  
L. E. Ocola ◽  
M. Green ◽  
T. Sorsch ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
Ring Structure ◽  
Channel Length ◽  
Low Energy ◽  
Gate Length ◽  
Direct Write ◽  
Mos Transistors ◽  
Processing Elements ◽  
Effective Channel

AbstractThis article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (∼ 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

An Effective SIMS Methodology for GOI Contamination Analysis

2013 ◽  
Author(s):  
Yanhua Huang ◽  
Lei Zhu ◽  
Kenny Ong ◽  
Hanwei Teo ◽  
Younan Hua
Keyword(s):  
Oxide Layer ◽  
Secondary Ion Mass Spectrometry ◽  
Gate Oxide ◽  
Sample Surface ◽  
Low Energy ◽  
Cross Contamination ◽  
Common Effect ◽  
Sims Analysis ◽  
Secondary Ion ◽  
Lower Background

Abstract Contamination in the gate oxide layer is the most common effect which cause the gate oxide integrate (GOI) issue. Dynamic Secondary Ion Mass Spectrometry (SIMS) is a mature tool for GOI contamination analysis. During the sample preparation, all metal and IDL layers above poly should be removed because the presence of these layers added complexity for the subsequent SIMS analysis. The normal delayering process is simply carried out by soaking the sample in the HF solution. However, the poly surface is inevitably contaminated by surroundings even though it is already a practice to clean with DI rinse and tape. In this article, TOFSIMS with low energy sputter gun is used to clean the sample surface after the normal delayering process. The residue signals also can be monitored by TOF SIMS during sputtering to confirm the cross contamination is cleared. After that, a much lower background desirable by dynamic SIMS. Thus an accurate depth profile in gate oxide layer can be achieved without the interference from surface.

Nitrogen (N2) Implantation to Suppress Growth of Interfacial Oxide in Mocvd Bst and Sputtered Bst Films

1999 ◽  
Vol 567 ◽  
Author(s):  
Renee Nieh ◽  
Wen-Jie Qi ◽  
Yongjoo Jeon ◽  
Byoung Hun Lee ◽  
Aaron Lucas ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Nitrogen Concentration ◽  
Chemical Vapor ◽  
Future Generation ◽  
Oxide Thickness ◽  
Layer Growth ◽  
X Ray ◽  
Bst Films

ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate dielectric in future generation devices. The biggest obstacle to scaling the equivalent oxide thickness (EOT) of BST is an interfacial layer, SixOy, which forms between BST and Si. Nitrogen (N2) implantation into the Si substrate has been proposed to reduce the growth of this interfacial layer. In this study, capacitors (Pt/BST/Si) were fabricated by depositing thin BST films (50Å) onto N2 implanted Si in order to evaluate the effects of implant dose and annealing conditions on EOT. It was found that N2 implantation reduced the EOT of RF magnetron sputtered and Metal Oxide Chemical Vapor Deposition (MOCVD) BST films by ∼20% and ∼33%, respectively. For sputtered BST, an implant dose of 1×1014cm−;2 provided sufficient nitrogen concentration without residual implant damage after annealing. X-ray photoelectron spectroscopy data confirmed that the reduction in EOT is due to a reduction in the interfacial layer growth. X-ray diffraction spectra revealed typical polycrystalline structure with (111) and (200) preferential orientations for both films. Leakage for these 50Å BST films is on the order of 10−8 to 10−5 A/cm2—lower than oxynitrides with comparable EOTs.

scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

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