International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)
Latest Publications

TOTAL DOCUMENTS

218

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Published By IEEE

0780370503

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Advantage of silicon nitride gate insulator transistor by using microwave excited high-density plasma for applying 100nm technology node

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979639 ◽

2005 ◽

Cited By ~ 2

Author(s):

S. Sugawa ◽

I. Ohshima ◽

H. Ishino ◽

Y. Saito ◽

M. Hirayama ◽

...

Keyword(s):

Silicon Nitride ◽

High Density ◽

Gate Insulator ◽

Technology Node ◽

Density Plasma

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Enhanced performance of strained Strained-Si MOSFETs on CMP sige virtual substrate

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979620 ◽

2005 ◽

Cited By ~ 8

Author(s):

N. Sugii ◽

D. Hisamoto ◽

K. Washio ◽

N. Yokoyama ◽

S. Kimura

Keyword(s):

Strained Si

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Robust 130 mn-node Cu dual damascene technology with low-k barrier SiCN

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979407 ◽

2002 ◽

Cited By ~ 2

Author(s):

H. Aoki ◽

K. Torii ◽

T. Oshima ◽

J. Noguchi ◽

U. Tanaka ◽

...

Keyword(s):

Dual Damascene ◽

Low K

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Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979649 ◽

2002 ◽

Cited By ~ 22

Author(s):

C.H. Liu ◽

M.T. Lee ◽

Chih-Yung Lin ◽

J. Chen ◽

K. Schruefer ◽

...

Keyword(s):

Gate Dielectrics ◽

Negative Bias ◽

Negative Bias Temperature Instability ◽

Temperature Instability ◽

Bias Temperature Instability

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CMOS device optimization for mixed-signal technologies

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979469 ◽

2002 ◽

Cited By ~ 32

Author(s):

P.A. Stolk ◽

H.P. Tuinhout ◽

R. Duffy ◽

E. Augendre ◽

L.P. Bellefroid ◽

...

Keyword(s):

Mixed Signal ◽

Device Optimization

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Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979562 ◽

2002 ◽

Cited By ~ 19

Author(s):

E. Beyne

Keyword(s):

Vlsi Circuits ◽

Next Generation ◽

Electrical Interconnects ◽

High Bandwidth ◽

Very High

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Experimental evidence of hydrogen-related SILC generation in thin gate oxide

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979449 ◽

2002 ◽

Cited By ~ 2

Author(s):

Y. Mitani ◽

H. Satake ◽

A. Toriumi

Keyword(s):

Experimental Evidence ◽

Gate Oxide ◽

Thin Gate Oxide

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Investigations of stress sensitivity of 0.12 CMOS technology using process modeling

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979642 ◽

2002 ◽

Cited By ~ 3

Author(s):

V. Senez ◽

T. Hoffmann ◽

E. Robilliart ◽

G. Bouche ◽

H. Jaouen ◽

...

Keyword(s):

Process Modeling ◽

Cmos Technology ◽

Stress Sensitivity

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Integration of porous ultra low-k dielectric with CVD barriers

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979416 ◽

2002 ◽

Cited By ~ 3

Author(s):

K. Mosig ◽

H. Cox ◽

E. Klawuhn ◽

T. Suwwan de Felipe ◽

A. Shiota

Keyword(s):

Low K

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Analyzing the effects of floating dummy-fills: from feature scale analysis to full-chip RC extraction

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979600 ◽

2002 ◽

Cited By ~ 1

Author(s):

Keun-Ho Lee ◽

Jin-Kyu Park ◽

Young-Nam Yoon ◽

Dai-Hyun Jung ◽

Jai-Pil Shin ◽

...

Keyword(s):

Scale Analysis ◽

Feature Scale

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International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Advantage of silicon nitride gate insulator transistor by using microwave excited high-density plasma for applying 100nm technology node

Enhanced performance of strained Strained-Si MOSFETs on CMP sige virtual substrate

Robust 130 mn-node Cu dual damascene technology with low-k barrier SiCN

Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics

CMOS device optimization for mixed-signal technologies

Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits

Experimental evidence of hydrogen-related SILC generation in thin gate oxide

Investigations of stress sensitivity of 0.12 CMOS technology using process modeling

Integration of porous ultra low-k dielectric with CVD barriers

Analyzing the effects of floating dummy-fills: from feature scale analysis to full-chip RC extraction

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)
Latest Publications