Triggering and Suppression of Soft Breakdown During Mercury-Probe Assessment of Thin Gate Oxide Quality

1999 ◽  
Vol 567 ◽  
Author(s):  
S. Evseev ◽  
A. Cacciato
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Oxide Layers ◽  
Current Stress ◽  
Thin Gate Oxide ◽  
Soft Breakdown ◽  
Microelectronic Manufacturing ◽  
Routine Assessment ◽  
Probe Measurements ◽  
Gate Oxide Integrity

ABSTRACTThe breakdown of ultra-thin gate oxide layers is investigated using fast-feedback Hg-probe measurements to perform Exponentially Ramped Current Stress (ERCS) tests. Several parameters have been varied in the ERCS test: oxide thickness (4nm, 5nm, 6nm and 7nm), capacitor area (0.12cm2 and 0.023cm2) and initial injected current (5×10−5 A and 5×10−4 A). Soft breakdown is detected only in case of oxides thinner than 5 nm. It is found that the fraction of points on the wafer on which soft breakdown occurs reduces by increasing the value of the injected current at the beginning of the ERCS test or completely disappears by decreasing the capacitor area. Consequences of current results for correct routine assessment of gate oxide integrity in microelectronic manufacturing are discussed.

Modeling Soft Breakdown of Ultra-Thin Gate Oxide Layers

1999 ◽  
Vol 567 ◽  
Author(s):  
Michel Houssa ◽  
P.W. Mertens ◽  
M.M. Heyns
Keyword(s):  
Gate Voltage ◽  
Dielectric Breakdown ◽  
Percolation Cluster ◽  
Gate Oxide ◽  
Oxide Layers ◽  
Long Range Correlations ◽  
Electrical Stress ◽  
Non Gaussian ◽  
Thin Gate Oxide ◽  
Soft Breakdown

ABSTRACTThe time-dependent dielectric breakdown of MOS capacitors with ultra-thin gate oxide layers is investigated. After the occurrence of soft breakdown, the gate current increases by 3 to 4 orders of magnitudes and behaves like a power law of the applied gate voltage. It is shown that this behavior can be explained by assuming that a percolation path is formed between the electron traps generated in the gate oxide layer during electrical stress of the capacitors. The time dependence of the gate voltage signal after soft breakdown is next analysed. It is shown that the fluctuations in the gate voltage are non-gaussian as well as that long-range correlations exist in the system after soft breakdown. These results can be explained by a dynamic percolation model, taking into account the trapping-detrapping of charges within the percolation cluster formed at soft breakdown.

Soft breakdown of ultra-thin gate oxide layers

1996 ◽  
Vol 43 (9) ◽  
pp. 1499-1504 ◽  
Author(s):  
M. Depas ◽  
T. Nigam ◽  
M.M. Heyns
Keyword(s):  
Gate Oxide ◽  
Oxide Layers ◽  
Thin Gate Oxide ◽  
Soft Breakdown

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li
Keyword(s):  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Integral Approach ◽  
Predicting Model ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Novel Theory ◽  
Gate Tunneling ◽  
Thin Gate Oxide

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

Effects of Silicon Ion Implantation upon Thin Gate Oxide Integrity

1992 ◽  
Vol 262 ◽  
Author(s):  
G. -S. Lee ◽  
J. -G. Park ◽  
S. -P. Choi ◽  
C. -H. Shin ◽  
Y. -B. Sun ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Surface Region ◽  
Gate Oxide ◽  
Near Surface ◽  
Time Dependent Dielectric Breakdown ◽  
Thin Gate Oxide ◽  
Si Ion Implantation ◽  
Gate Oxide Integrity

ABSTRACTIn this study, using oxide breakdown voltage and time-dependent-dielectric breakdown measurements, thermal wave modulated reflectance and chemical etching/optical microscopy, we investigated effects of Si ion implantation upon formation of D-defects and thin gate oxide integrity. Our data show that addition of Si ion implantation with a dose of up to 1013 ions/cm2 improves oxide integrity if the implantation is done at a certain step just before sacrificial oxidation in the Mb DRAM process. However, no improvement in oxide integrity is observed when the same implantation is done on the virgin wafer surfaces at the start of the same Mb DRAM process. We discuss our hypothesis that the improvement in oxide integrity is due to a reduction in the D-defect density in the near-surface region of the wafer.

Effects of D-Defects in CZ Silicon Upon Thin Gate Oxide Integrity

1993 ◽  
pp. 289-298 ◽  
Author(s):  
J.-G. Park ◽  
S.-P. Choi ◽  
G.-S. Lee ◽  
Y.-J. Jeong ◽  
Y.-S. Kwak ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Thin Gate Oxide ◽  
Gate Oxide Integrity
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