Solutions to Gate Oxide Integrity on TFSOI Substrates Caused by PMOS Threshold-Voltage Implant

1998 ◽  
Vol 510 ◽  
Author(s):  
S. Q. Hong ◽  
T. Wetteroth ◽  
S. R. Wilson ◽  
B. Steele ◽  
D. K. Schroder
Keyword(s):  
Threshold Voltage ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Oxide Growth ◽  
Oxide Breakdown ◽  
Oxide Degradation ◽  
Process Damage ◽  
Gate Oxide Integrity

AbstractDue to the lack of effective gettering, gate oxide on thin-film-silicon-on-insulator (TFSOI) substrates is much more sensitive than its bulk Si counterpart to process damage during device fabrication, especially prior to gate oxide growth. Presented in this paper as a typical example is the severe oxide degradation caused by PMOS threshold-voltage implant. Several approaches to circumvent this problem are explored, such as Vt implant without sacrificial oxide (sacox), low temperature anneal before sacox removal, or implementation of lateral gettering. As a result of these efforts, a significant improvement in gate oxide integrity is achieved with increased oxide breakdown voltages and charge-to-breakdowns, as well as a reduction in oxide charge trapping. This work also demonstrates the feasibility of achieving bulk-comparable gate oxide on TFSOI substrates.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Compatibility of POCl3 Gate Process with the Fabrication of Vertical 4H-SiC MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 565-570
Author(s):  
Tomokatsu Watanabe ◽  
Munetaka Noguchi ◽  
Shingo Tomohisa ◽  
Naruhisa Miura
Keyword(s):  
Thermal Treatment ◽  
Low Temperature ◽  
Negative Charge ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Fabrication ◽  
Post Processing ◽  
Production Lines ◽  
Channel Mobility ◽  
Device Operation

We used the POCl3 gate technique for the fabrication of 4H-SiC vertical MOSFETs, and examined its effect on the VTH-RON tradeoff and the compatibility with device fabrication. The gate oxide film was formed by thermal dry O2 oxidation followed by POCl3 or NO annealing. The POCl3 process reduced RON by about 30% compared with the NO process for the ones having VTH of 1.1 V, being attributed to the channel mobility enhancement. Moreover, the improvement was more effective for higher VTH designs. The conventional thermal treatment after the gate process considerably spoiled the channel mobility improvement brought by the POCl3 annealing and strengthened negative charge trapping in the gate oxide. The presumed extra-formed defects also affected the EOX dependence of tBD on the TDDB tests, being expected to shorten the gate oxide lifetime under practical device operation stress. Successful insertion of the POCl3 process into production lines depends upon careful low-temperature post processing.

Dependence of gate oxide breakdown on initial charge trapping under Fowler-Nordheim injection

1998 ◽  
Vol 38 (6-8) ◽  
pp. 1091-1096
Author(s):  
A. Martin ◽  
R. Duane ◽  
P. O'Sullivan ◽  
A. Mathewson
Keyword(s):  
Charge Trapping ◽  
Gate Oxide ◽  
Oxide Breakdown ◽  
Initial Charge

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

2020 ◽  
Vol 1004 ◽  
pp. 554-558
Author(s):  
Kwangwon Lee ◽  
Young Ho Seo ◽  
Taeseop Lee ◽  
Kyeong Seok Park ◽  
Martin Domeij ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Bias ◽  
Annealed Condition ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
Phosphorus Doped ◽  
Gate Bias Stress ◽  
Gate Oxide Integrity

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

2013 ◽  
Vol 10 (4) ◽  
pp. 150-154 ◽  
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Leakage Currents ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Operation Temperature

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

Performance of Poly-Si Tfts with Double Gate Oxide Layers

1996 ◽  
Vol 424 ◽  
Author(s):  
Byung-Hyuk Min ◽  
Cheol-Min Park ◽  
Jae-Hong Jun ◽  
Byung-Sung Bae ◽  
Min-Koo Han
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Insulator ◽  
Double Gate ◽  
Electrical Parameters ◽  
Electrical Field ◽  
Oxide Layers ◽  
Oxide Breakdown ◽  
Electrical Stress ◽  
Low Threshold

AbstractWe have fabricated a poly-Si TFT with double gate insulator composed of ECR oxide and APCVD oxide to improved the performance of poly-Si TFTs. The poly-Si TFT with double gate oxide exhibits the remarkable enhancement of the electrical parameters compared with the conventional poly-Si TFTs which has APCVD gate oxide, such as improvement of the subthreshold swing and the low threshold voltage. The proposed poly-Si TFT has a higher oxide breakdown electrical field and the device characteristics are not degraded significantly after an electrical stress. It is found that the ECR oxide plays a key role to improve the device performances and prevent the poly-Si TFTs from degradation due to the electrical stress.

Improvement of Gate Oxide Integrity in Low Temperature Poly Silicon TFT

2003 ◽  
Vol 762 ◽  
Author(s):  
Seok-Woo Lee ◽  
Dae Hyun Nam ◽  
Jin Mo Yoon ◽  
Hyun Sik Seo ◽  
Kyoung Moon Lim ◽  
...  
Keyword(s):  
Elevated Temperature ◽  
Deep Level ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Electrical Characteristics ◽  
Subthreshold Slope ◽  
Mos Capacitors ◽  
Oxide Charge ◽  
Oxide Deposition ◽  
Gate Oxide Integrity

AbstractThe electrical characteristics of SiH4-based PECVD gate oxide have been investigated with respect to gate oxide integrity (GOI) and its reliability. It was found that the GOI of poly-Si TFT integrated on glass substrate strongly depended on the charge trapping and deep level interface states generation under Fowler-Nordheim stress (FNS). By applying elevated temperature postanneal without vacuum break after the gate oxide deposition, highly reliable gate oxide was obtained. Under FNS, ID-VG curve showed severe shift and degradation of subthreshold slope, which were reduced by adopting post-annealed gate oxide. Besides, the TFT with post-annealed gate oxide showed around 10 times higher charge to breakdown than that of as-deposited gate oxide. Charge to breakdown of MOS capacitors were also studied. By applying post-annealed gate oxide, charge to breakdown drastically improved, which could be explained by reduced charge trapping under FNS.

Improvement in gate oxide integrity on thin-film silicon-on-insulator substrates by lateral gettering

1997 ◽  
Vol 71 (23) ◽  
pp. 3397-3399 ◽  
Author(s):  
S. Q. Hong ◽  
T. Wetteroth ◽  
H. Shin ◽  
S. R. Wilson ◽  
D. Werho ◽  
...  
Keyword(s):  
Thin Film ◽  
Gate Oxide ◽  
Silicon On Insulator ◽  
Thin Film Silicon ◽  
Gate Oxide Integrity
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