Performance of Poly-Si Tfts with Double Gate Oxide Layers

1996 ◽  
Vol 424 ◽  
Author(s):  
Byung-Hyuk Min ◽  
Cheol-Min Park ◽  
Jae-Hong Jun ◽  
Byung-Sung Bae ◽  
Min-Koo Han
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Insulator ◽  
Double Gate ◽  
Electrical Parameters ◽  
Electrical Field ◽  
Oxide Layers ◽  
Oxide Breakdown ◽  
Electrical Stress ◽  
Low Threshold

AbstractWe have fabricated a poly-Si TFT with double gate insulator composed of ECR oxide and APCVD oxide to improved the performance of poly-Si TFTs. The poly-Si TFT with double gate oxide exhibits the remarkable enhancement of the electrical parameters compared with the conventional poly-Si TFTs which has APCVD gate oxide, such as improvement of the subthreshold swing and the low threshold voltage. The proposed poly-Si TFT has a higher oxide breakdown electrical field and the device characteristics are not degraded significantly after an electrical stress. It is found that the ECR oxide plays a key role to improve the device performances and prevent the poly-Si TFTs from degradation due to the electrical stress.

The Poly-Si Tfts Fabricated by Novel Oxidation Method with Intermediate Oxide

1996 ◽  
Vol 424 ◽  
Author(s):  
C-M Park ◽  
J-S Yoo ◽  
B-H Min ◽  
M-K Han
Keyword(s):  
Surface Roughness ◽  
Oxide Layer ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Dielectric Strength ◽  
Device Performance ◽  
Electrical Parameters ◽  
Oxidation Method ◽  
Electrical Stress ◽  
Intermediate Oxide

AbstractWe have fabricated a poly-Si TFT using a novel oxidation method, which improves the surface roughness at the interface between the poly-Si layer and the gate oxide layer. Compared with the poly-Si TFTs fabricated by the conventional oxidation method, the proposed poly-Si TFT exhibits the remarkable enhancement of the electrical parameters, such as the subthreshold swing and the threshold voltage. It is observed that the proposed poly-Si TFT has a higher dielectric strength and the device characteristics are not degraded significantly after an electrical stress. The improvement of the surface roughness at oxide/poly-Si interface is found to be critical to enhance the device performance.

Real-Time External Compensation of Threshold Voltage Shift Using Double-Gate Oxide TFTs in a Gate Driving System

2016 ◽  
Vol 12 (9) ◽  
pp. 892-897 ◽  
Author(s):  
Bong-Hyun You ◽  
Soo-Yeon Lee ◽  
Seok-Ha Hong ◽  
Jae-Hoon Lee ◽  
Hyun-Chang Kim ◽  
...  
Keyword(s):  
Real Time ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Double Gate ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Driving System ◽  
Oxide Tfts ◽  
Gate Driving

Modeling Soft Breakdown of Ultra-Thin Gate Oxide Layers

1999 ◽  
Vol 567 ◽  
Author(s):  
Michel Houssa ◽  
P.W. Mertens ◽  
M.M. Heyns
Keyword(s):  
Gate Voltage ◽  
Dielectric Breakdown ◽  
Percolation Cluster ◽  
Gate Oxide ◽  
Oxide Layers ◽  
Long Range Correlations ◽  
Electrical Stress ◽  
Non Gaussian ◽  
Thin Gate Oxide ◽  
Soft Breakdown

ABSTRACTThe time-dependent dielectric breakdown of MOS capacitors with ultra-thin gate oxide layers is investigated. After the occurrence of soft breakdown, the gate current increases by 3 to 4 orders of magnitudes and behaves like a power law of the applied gate voltage. It is shown that this behavior can be explained by assuming that a percolation path is formed between the electron traps generated in the gate oxide layer during electrical stress of the capacitors. The time dependence of the gate voltage signal after soft breakdown is next analysed. It is shown that the fluctuations in the gate voltage are non-gaussian as well as that long-range correlations exist in the system after soft breakdown. These results can be explained by a dynamic percolation model, taking into account the trapping-detrapping of charges within the percolation cluster formed at soft breakdown.

scholarly journals Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

2019 ◽  
Vol 9 (1) ◽  
pp. 163
Author(s):  
Hakkee Jung
Keyword(s):  
Threshold Voltage ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Double Gate ◽  
Short Channel ◽  
Double Gate Mosfet ◽  
Channel Effects ◽  
Channel Thickness

Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

Solutions to Gate Oxide Integrity on TFSOI Substrates Caused by PMOS Threshold-Voltage Implant

1998 ◽  
Vol 510 ◽  
Author(s):  
S. Q. Hong ◽  
T. Wetteroth ◽  
S. R. Wilson ◽  
B. Steele ◽  
D. K. Schroder
Keyword(s):  
Threshold Voltage ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Oxide Growth ◽  
Oxide Breakdown ◽  
Oxide Degradation ◽  
Process Damage ◽  
Gate Oxide Integrity

AbstractDue to the lack of effective gettering, gate oxide on thin-film-silicon-on-insulator (TFSOI) substrates is much more sensitive than its bulk Si counterpart to process damage during device fabrication, especially prior to gate oxide growth. Presented in this paper as a typical example is the severe oxide degradation caused by PMOS threshold-voltage implant. Several approaches to circumvent this problem are explored, such as Vt implant without sacrificial oxide (sacox), low temperature anneal before sacox removal, or implementation of lateral gettering. As a result of these efforts, a significant improvement in gate oxide integrity is achieved with increased oxide breakdown voltages and charge-to-breakdowns, as well as a reduction in oxide charge trapping. This work also demonstrates the feasibility of achieving bulk-comparable gate oxide on TFSOI substrates.

scholarly journals Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET

2021 ◽  
Vol 11 (1) ◽  
pp. 232
Author(s):  
Hakkee Jung
Keyword(s):  
Threshold Voltage ◽  
Gate Voltage ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Length ◽  
Double Gate ◽  
Static Feedback ◽  
Silicon Thickness ◽  
Relationship Of ◽  
Bottom Gate

The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L) × 10-7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtained. As a result, we observe the DIBL is proportional to the negative third power of the channel length and the second power of the silicon thickness and linearly proportional to the geometric mean of the top and bottom gate oxide thicknesses, and derive a relation such as DIBL =25.15ηL_g^(-3) t_si^2 √(t_ox1∙t_ox2 ), where η is a static feedback coefficients between 0 and 1. The η is found to be between 0.5 and 1.0 in this model. The DIBL model of this paper has been observed to be in good agreement with the result of other paper, so it can be used in circuit simulation such as SPICE.

Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges

2015 ◽  
Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong
Keyword(s):  
Failure Analysis ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Analysis Approach ◽  
Test Results ◽  
Root Cause ◽  
Switching Event ◽  
Output Transistor ◽  
Event Based ◽  
Trapped Charge

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.

A Study of Pad Contamination Defect and Removal

2008 ◽  
Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Oxide ◽  
Action Plans ◽  
Preventive Action ◽  
Oxide Breakdown ◽  
Reliability Level ◽  
The Future ◽  
Dry Etch ◽  
Removal Technique

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

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