Silicon Etching in Rapid Thermal Chemical Vapor Deposition of Tisi2

Downscaling of microelectronics devices into the deep submicron regime requires ultrashallow junctions with reliable, low-resistivity contacts. The conventional self-aligned TiSi2 technology exhibits a serious limitation in forming contacts to ultra-shallow junctions due to silicon substrate consumption. Selective chemical vapor deposition of TiSi2 is being investigated because of its potential for overcoming this difficulty. In this process Si and Ti are supplied from the gas phase. The standard source gas for Ti has been TiCl4 while several gases including SiH4, Si2H6 and SiH2Cl2 are available for Si. The reports on this process indicate that optimized process conditions can deliver TiSi2 films without substrate consumption. Although this promise is significant, the deposition has a complicated chemistry involving processes such as silicon etching, silicon consumption or silicon pedestal deposition taking place along with TiSi2 deposition. Although, suppression of Si-substrate etching by excess H2 has been reported previously, a broad quantitative analysis has been lacking up until this reporting. In this work, we have examined silicon etching trends as a function of temperature for different H2:TiCl4 flow ratios using thermodynamic equilibrium calculations. We have also performed experiments in a lamp heated rapid thermal chemical vapor deposition reactor to study substrate etching over the temperature range of 600°C to 800°C and for H2 flows from 0 to 1000 sccm. A silicon conversion efficiency is defined as a measure of the amount of Si converted to TiSi2 relative to total Si used from the substrate and it is evaluated via both thermodynamic calculations and experiments with good agreement between the two. Our calculations suggest that at high temperatures, etching occurs mainly via formation of SiCl2. Addition of H2 into the reaction chemistry encourages formation of HCl reducing the amount of Cl available for SiCl2 formation responsible for substrate etching. Our results show that by optimizing the H2 flow rate and the process temperature silicon substrate etching can be effectively suppressed.