Characteristics of Arsenic Doped Polycrystalline Silicon-Gate Capacitors After Rapid Thermal Processing

1987 ◽  
Vol 106 ◽  
Author(s):  
R. Angelucci ◽  
C. Y. Wong ◽  
J. Y.-C. Sun ◽  
G. Scilla ◽  
P. A. McFarland ◽  
...  
Keyword(s):  
Work Function ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Polycrystalline Silicon ◽  
Rapid Thermal Processing ◽  
Interface States ◽  
Fixed Charges ◽  
Polysilicon Gate

ABSTRACTThe feasibility and advantages of using rapid thermal annealing to achieve a proper n+ polysilicon work function are demonstrated. Our data shows that RTA can be used to activate arsenic in the polysilicon gate after a regular furnace anneal or to diffuse and activate arsenic without any prior furnace anneal. Interface states and fixed charges due to RTA can be annealed out at 500°C for 30 min in forming gas. New insights into the diffusion, segregation, and activation of As in polysilicon during furnace and/or rapid thermal annealing have been obtained.

Rapid Thermal Annealing and Oxidation of Silicon Wafers with Back-Side Films

1997 ◽  
Vol 470 ◽  
Author(s):  
A. T. Fiory
Keyword(s):  
Thermal Oxidation ◽  
Sheet Resistance ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Temperature Control ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Back Side ◽  
Control Accuracy

ABSTRACTTemperatures for lamp-heated rapid thermal processing of wafers with various back-side films were controlled by a Lucent Technologies pyrometer which uses a/c lamp ripple to compensate for emissivity. Process temperatures for anneals of arsenic and boron implants were inferred from post-anneal sheet resistance, and for rapid thermal oxidation, from oxide thickness. Results imply temperature control accuracy of 12°C to 17°C at 3 standard deviations.

Characterisation of Low Energy Boron Implantation and Fast Ramp-Up Rapid Thermal Annealing

1998 ◽  
Vol 525 ◽  
Author(s):  
E. J. H. Collart ◽  
G. de Cock ◽  
A. J. Murrell ◽  
M. A. Foad
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Low Energy ◽  
Electrical Activation ◽  
Junction Depth ◽  
Boron Implantation

ABSTRACTThe effects of ramp-up rate during rapid thermal processing of ultra-shallow boron implants have been investigated. Ramp-up rates were varied between 25 °C and 200 °C for two types of anneals: soak anneals and spike anneals. It was found that the ramp-up rate had very little influence on junction depth or electrical activation for both types of anneals. Spike anneals did produce shallower profiles than soak anneal for a comparable electrical activation and may be an option for future processes.

Characterization of Doped Si-TiSi2 Bilayers Formed by Ion Beam Mixing and Rapid Thermal Annealing

1985 ◽  
Vol 45 ◽  
Author(s):  
K. Maex ◽  
R.F. de Keersmaecker ◽  
P.F.A. Alkemade
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Ion Beam ◽  
Rapid Thermal Processing ◽  
Ion Beam Mixing ◽  
Simultaneous Formation ◽  
Impurity Redistribution

ABSTRACTThe use of rapid thermal processing is reported for simultaneous formation of TiSi2 from Ti deposited layers and activation of As or Sb implanted profiles in Si. Properties of the silicide and the doped Si are reported with emphasis on impurity redistribution and defect removal.

Rapid Thermal Processing of Thin Film Electroluminescent Display Materials

1988 ◽  
Vol 100 ◽  
Author(s):  
D. M. Kim ◽  
F. Qian ◽  
R. Solanki ◽  
R. T. Tuenge ◽  
C. N. King
Keyword(s):  
Thin Film ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Annealing Temperature ◽  
Rapid Thermal Processing ◽  
Processing Conditions ◽  
Furnace Annealing ◽  
Fatigue Effect

ABSTRACTRapid thermal annealing of the electroluminescent phosphors ZnS:Mn, SrS:CeF3 and ZnS:SmCl3 has been examined as a function of annealing temperature (500–750°C) and time of exposure (10–120 sec.). The resulting brightness and efficiency of luminescence are correlated with the different processing conditions used. The results indicate that the brightness can be significantly improved from the value obtained with furnace annealing without causing film delamination, blistering or fatigue effect.

Polycrystalline Silicon Emitter Contacts Formed by Rapid Thermal Annealing

1989 ◽  
Vol 136 (1) ◽  
pp. 215-224 ◽  
Author(s):  
M. Delfino ◽  
J. G. de Groot ◽  
K. N. Ritz ◽  
P. Maillot
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Polycrystalline Silicon

Rapid Thermal Annealing of Ni/Al/Si and Ni/Si Systems

1986 ◽  
Vol 74 ◽  
Author(s):  
A. Katz ◽  
Y. KOMEM
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Reference System ◽  
Diffusion Processes ◽  
Eutectic Temperature ◽  
Melting Process ◽  
Polycrystalline Layer ◽  
Smooth Interface ◽  
And Diffusion

AbstractThe effect of Rapid Thermal Annealing on phase formation and diffusion processes in the Ni(30 nm) /Al(10 nm)/Si system was studied and coxpared to a Ni(30 nm)/Si reference system. Heat treatments were carried out at temperatures between 400°C and 900°C for 2 seconds.The results obtained by means of TEM, AES and XRD indicated that the Ni/Al/Si system underwent a local melting in the intermediate Al layer at the Al/Si eutectic temperature (577°C). This reaction, due to the rapid melting process, resulted in formation of a unique layered-structure composed of a columnar polycrystalline layer (60 nm thick) of Ni2Si and NiSi adjacent to the Si substrate with relatively smooth interface and an outer layer of two separate polycrystalline films (both about 10 m thick) of Al3Ni (inside) and Ni(Al0.5Si0.5 ) (outside). Under the same rapid thermal processing conditions the Ni/Si reference system underwent a solid state reaction which resulted in the formation of a polycrystalline layer (60 nm thick) composed of Ni2Si and NiSi as well as NiSi2.

Silicon Recrystallization in Sipos Material Obtained by Disilane

1995 ◽  
Vol 403 ◽  
Author(s):  
J. J. Pedroviejo ◽  
B. Garrido ◽  
J. C. Ferrer ◽  
A. Cornet ◽  
E. Scheid ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Vapor Deposition ◽  
Polycrystalline Silicon ◽  
Chemical Vapor ◽  
Low Pressure ◽  
Thermal Treatments ◽  
Structural Modifications ◽  
Pressure Chemical

AbstractConventional and Rapid Thermal Annealing of Semi-Insulating Polycrystalline Silicon layers obtained by Low Pressure Chemical Vapor Deposition (LPCVD) from disilane Si2H6 have been performed in order to determine the structural modifications induced on the layers by these thermal treatments. The study of these modifications has been carried out by several analysis methods like FTIR, XPS, TEM, RAMAN and ellipsometry. The results obtained are presented, contrasted and discussed in this work.

Stability of Ultra-Thin Gate Oxides with Boron Doped Polysilicon Gate Structures After Rapid Thermal Annealing

1993 ◽  
Vol 303 ◽  
Author(s):  
Bojun Zhang ◽  
Dennis M. Maher ◽  
Mark S. Denker ◽  
Mark A. Ray
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Depth Profiling ◽  
Gate Oxide ◽  
Annealing Condition ◽  
Dopant Diffusion ◽  
Boron Diffusion ◽  
Gate Oxides ◽  
Diffusion Behavior ◽  
Polysilicon Gate

ABSTRACTWe report a systematic study of dopant diffusion behavior for thin gate oxides and polysilicon implanted gate structures. Boron behavior is emphasized and its behavior is compared to that of As+ and BF2+. Dopant activation is achieved by rapid thermal annealing. Test structures with 100 Å, 60 Å and 30 Å gate oxides and ion implanted polysilicon gate electrodes were fabricated and characterized after annealing by SIMS, SEM, TEM, and C-V rpeasurements. For arsenic implanted structures, no dopant diffusion through a gate oxide of 30 Å thickness and an annealing condition as high as 1 100*C/1Os was observed. For boron implanted structures, as indicated by SIMS depth profiling, structures annealed at 1000*C/10s exhibit a so-called critical condition for boron diffusion through a 30 Å gate oxide. Boron dopant penetration is clearly observed for 60 Å gate oxides at an annealing condition of 1050 0C/10s. The flatband voltage shift can be as high as 0.56 volts as indicated by C-V measurements for boron penetrated gate oxides. However, 100 Å gate oxides are good diffusion barriers for boron at an annealing condition of 1100°C/10s. For BF2 implanted structures, the diffusion behavior is consistent with behavior reported in the literature.

Sign in / Sign up

Export Citation Format

Share Document