Stability of Ultra-Thin Gate Oxides with Boron Doped Polysilicon Gate Structures After Rapid Thermal Annealing

1993 ◽  
Vol 303 ◽  
Author(s):  
Bojun Zhang ◽  
Dennis M. Maher ◽  
Mark S. Denker ◽  
Mark A. Ray
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Depth Profiling ◽  
Gate Oxide ◽  
Annealing Condition ◽  
Dopant Diffusion ◽  
Boron Diffusion ◽  
Gate Oxides ◽  
Diffusion Behavior ◽  
Polysilicon Gate

ABSTRACTWe report a systematic study of dopant diffusion behavior for thin gate oxides and polysilicon implanted gate structures. Boron behavior is emphasized and its behavior is compared to that of As+ and BF2+. Dopant activation is achieved by rapid thermal annealing. Test structures with 100 Å, 60 Å and 30 Å gate oxides and ion implanted polysilicon gate electrodes were fabricated and characterized after annealing by SIMS, SEM, TEM, and C-V rpeasurements. For arsenic implanted structures, no dopant diffusion through a gate oxide of 30 Å thickness and an annealing condition as high as 1 100*C/1Os was observed. For boron implanted structures, as indicated by SIMS depth profiling, structures annealed at 1000*C/10s exhibit a so-called critical condition for boron diffusion through a 30 Å gate oxide. Boron dopant penetration is clearly observed for 60 Å gate oxides at an annealing condition of 1050 0C/10s. The flatband voltage shift can be as high as 0.56 volts as indicated by C-V measurements for boron penetrated gate oxides. However, 100 Å gate oxides are good diffusion barriers for boron at an annealing condition of 1100°C/10s. For BF2 implanted structures, the diffusion behavior is consistent with behavior reported in the literature.

Measurement and modeling of boron diffusion in Si and strained Si1−xGexepitaxial layers during rapid thermal annealing

1993 ◽  
Vol 74 (9) ◽  
pp. 5520-5526 ◽  
Author(s):  
G. H. Loechelt ◽  
G. Tam ◽  
J. W. Steele ◽  
L. K. Knoch ◽  
K. M. Klein ◽  
...  
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Boron Diffusion

Rapid Thermal Annealing of As in Si

1989 ◽  
Vol 146 ◽  
Author(s):  
N.T. Shih ◽  
F.S. Huang ◽  
C.H. Chu ◽  
W.S. Chen
Keyword(s):  
Electric Field ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Chebyshev Polynomial ◽  
Depth Profiling ◽  
Electrical Characterization ◽  
Thermal Treatments ◽  
Hot Electron ◽  
Polynomial Distribution ◽  
Electron Effects

ABSTRACTThe results of a detailed investigation of diffusion of ion implanted As in Si during Rapid Thermal Annealing are reported. A series of experiments has been performed on samples prepared for various thermal treatments, such as peroxidation and preheat. The RTA conditions were chosen at 850°C for 15 seconds in order to study the metastable state. Sample analysis includes depth profiling by RBS and Spreading Resistance measurements, electrical characterization employing Hall measurements, and residual defects by cross-section TEM and planar image. The carrier concentration profile shows the different extent of the mixed Gaussian-Chebyshev polynomial distribution for various prepared samples. We believe the neutral interstitial state I°(Si) survives during RTA for asreceived samples. It gives a Gaussian curve in As profile. The denuded region produced after thermal treatments reduces the oxygen content and creates less 1°(Si) during SPE. So the Gaussian-Chebyshev polynomial distribution was obtained. From the above study, we believe the Gaussian profile can be obtained by controlling RTA conditions This Gaussian-like profile can also suppress hot electron effects by its smooth gradient (generating small electric field) near drain and large overlap under spacer (making large electric field away from gate). So we fabricated rapid thermal annealing singlediffusion drain n-MOSFET. The reduction of hot electron effects was studied, too.

X-Ray Induced Depth Profiling of Ion Implantations into Various Semiconductor Materials

2012 ◽  
Vol 195 ◽  
pp. 274-276 ◽  
Author(s):  
Philipp Hönicke ◽  
Matthias Müller ◽  
Burkhard Beckhoff
Keyword(s):  
Ion Implantation ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Measurement Techniques ◽  
Depth Profiling ◽  
Low Energy ◽  
Semiconductor Materials ◽  
Leakage Currents ◽  
X Ray ◽  
20 Nm

The continuing shrinking of the component dimensions in ULSI technology requires junction depths in the 20-nm regime and below to avoid leakage currents. These ultra shallow dopant distributions can be formed by ultra-low energy (ULE) ion implantation. However, accurate measurement techniques for ultra-shallow dopant profiles are required in order to characterize ULE implantation and the necessary rapid thermal annealing (RTA) processes.

A SIMS-TEM study of fluorine implants and anneals into silicon and polysilicon

1991 ◽  
Vol 49 ◽  
pp. 808-809
Author(s):  
Vidya S. Kaushik ◽  
Robert L. Hance ◽  
Hsing-H. Tseng ◽  
Philip J. Tobin
Keyword(s):  
Room Temperature ◽  
Gate Oxide ◽  
Wafer Surface ◽  
Boron Diffusion ◽  
Oxide Interface ◽  
Silicon Dioxide Layer ◽  
Diffusion Behavior ◽  
Polysilicon Layer ◽  
Sims Analysis ◽  
Implanted Devices

The behavior of fluorine in silicon is important for VLSI applications. The presence of fluorine can lead to improved gate oxide interface reliability and to enhanced boron diffusion in BF2 implanted devices. We have therefore studied the diffusion behavior of fluorine in silicon and polysilicon using coupled SIMS and TEM investigations on samples implanted with fluorine alone.Fluorine was implanted into a) (100) silicon and b) polysilicon layers to a dose of 1 x 1016/cm2 at 60 keV at room temperature. The polysilicon layers were grown by LPCVD at 635°C, resulting in small grained columnar polysilicon. The polysilicon layers had a 50 nm grown oxide layer between the polysilicon layer and the (100) silicon substrate. After the fluorine implants, the wafers were subjected to annealing at 750-950°C for 30 minutes. All the wafers were capped with a 13 nm silicon dioxide layer at the wafer surface prior to the ion implantation. SIMS analysis was performed on a Cameca IMS-3F spectrometer with 10 keV O2+ ions. XTEM images were obtained on a JEOL 2000 FXII operated at 200 keV with the electron beam parallel to the <110> silicon zone axis.

Characteristics of Arsenic Doped Polycrystalline Silicon-Gate Capacitors After Rapid Thermal Processing

1987 ◽  
Vol 106 ◽  
Author(s):  
R. Angelucci ◽  
C. Y. Wong ◽  
J. Y.-C. Sun ◽  
G. Scilla ◽  
P. A. McFarland ◽  
...  
Keyword(s):  
Work Function ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Polycrystalline Silicon ◽  
Rapid Thermal Processing ◽  
Interface States ◽  
Fixed Charges ◽  
Polysilicon Gate

ABSTRACTThe feasibility and advantages of using rapid thermal annealing to achieve a proper n+ polysilicon work function are demonstrated. Our data shows that RTA can be used to activate arsenic in the polysilicon gate after a regular furnace anneal or to diffuse and activate arsenic without any prior furnace anneal. Interface states and fixed charges due to RTA can be annealed out at 500°C for 30 min in forming gas. New insights into the diffusion, segregation, and activation of As in polysilicon during furnace and/or rapid thermal annealing have been obtained.

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