Mechanisms overview of Thermocompression Process for Copper Metal Bonding

2013 ◽  
Vol 1559 ◽  
Author(s):  
Paul Gondcharton ◽  
Floriane Baudin ◽  
Lamine Benaissa ◽  
Bruno Imbert
Keyword(s):  
Functional Integration ◽  
Pure Copper ◽  
Surface Preparation ◽  
Native Oxide ◽  
Process Window ◽  
Wafer Level ◽  
Metallic Oxide ◽  
Copper Diffusion ◽  
Thermomechanical Stress ◽  
Metal Bonding

ABSTRACTWafer level metal bonding involving copper material is widely used to achieve 3D functional integration of ICs and ensure effective packaging sealing for various applications. In this paper we focus on thermocompression bonding technology where temperature and pressure are used in parallel to assist the bonding process. More specifically a broad range of conditions was explored and interesting results were observed and are reported. Indeed, despite a relatively high roughness, the presence of a native oxide and the lack of surface preparation, there still exists a process window where wafer level bonding is allowed. In these conditions, limiting the bonding mechanisms to basic copper diffusion is no longer satisfactory. In this study, a specific scenario inspired by both wafer bonding and metal welding state of the art is put forward. Accordingly, pure copper diffusion through the bonding interface is lined with plastic deformation and metallic oxide fracture. In addition, polycrystalline film deformation due to thermomechanical stress is highlighted and grain growth and voiding formation are observed and confirmed.

scholarly journals Material Deformation Behavior in T-Shape Hydroforming of Metal Microtubes

Metals ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 199 ◽  
Author(s):  
Hajime Yasui ◽  
Shoichiro Yoshihara ◽  
Shigeki Mori ◽  
Kazuo Tada ◽  
Ken-ichi Manabe
Keyword(s):  
Pure Copper ◽  
Material Behavior ◽  
Tube Length ◽  
Process Window ◽  
Forming Limit ◽  
Outer Diameter ◽  
Friction Resistance ◽  
Buckling Resistance ◽  
The Many ◽  
Forming Defects

In this study, the material behavior in the T-shape microtube hydroforming (MTHF) of pure copper and stainless-steel SUS304 microtubes with an outer diameter of 500 µm and wall thickness of 100 µm was examined experimentally and numerically. This paper elucidates the basic deformation characteristics, the forming defects, and the forming limit as well as the effects of lubrication/friction and tube length. The hydroformability (bulge height) of the SUS304 microtube was shown to be higher than that of the copper microtube because of the high buckling resistance of SUS304. Good lubrication experimentally led to the high hydroformability of T-shape forming. The length of the microtube significantly affects its hydroformability. Friction resistance increases with increasing tube length and restricts the flow of the microtube material into the die cavity. By comparing the T-shape and cross-shape MHTF characteristics, we verified the hydroformability of the T-shape microtube to be superior to that of the cross-shape microtube theoretically and experimentally. In addition, the process window for T-shape MTHF had a narrower “success” area and wider buckling and folding regions than that for cross-shape MTHF. Furthermore, conventional finite element (FE) modeling without consideration of the grains was valid for MTHF processes owing to the many grains in the thickness direction.

Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers

2006 ◽  
Vol 970 ◽  
Author(s):  
Ronald J. Gutmann ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu
Keyword(s):  
Bonding Strength ◽  
Adhesive Bonding ◽  
Process Integration ◽  
Three Dimensional ◽  
Adhesive Layer ◽  
Wafer Level ◽  
Technology Platform ◽  
Metal Bonding ◽  
Wafer Level Packaging ◽  
Metal Metal

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.

The Interface Properties of La2O3/GaAs System by Surface Passivation

2012 ◽  
Vol 557-559 ◽  
pp. 1815-1818 ◽  
Author(s):  
Ting Ting Jia ◽  
Xing Hong Cheng ◽  
Duo Cao ◽  
Da Wei Xu ◽  
You Wei Zhang ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Surface Passivation ◽  
Gate Dielectric ◽  
Surface Preparation ◽  
Atomic Layer ◽  
Native Oxide ◽  
Atomic Force ◽  
Transmission Electron ◽  
Layer Deposition

In this work, La2O3 gate dielectric film was deposited by plasma enhanced atomic layer deposition. we investigate the effect of surface preparation of GaAs substrate, for example, native oxide, S-passivation, and NH3 plasma in situ treatment. The interfacial reaction mechanisms of La2O3 on GaAs is studied by means of X-ray photoelectron spectroscopy(XPS), high-resolution transmission electron microscopy(HRTEM) and atomic force microscope (AFM). As-O bonding is found to get effectively suppressed in the sample GaAs structures with both S-passivation and NH3 plasma surface treatments.

Common Themes in ther Epitaxial Growth of Oxides on Semiconductors

1994 ◽  
Vol 341 ◽  
Author(s):  
E. J. Tarsa ◽  
K. L. Mccormick ◽  
J. S. Speck
Keyword(s):  
Surface Preparation ◽  
Oxide Phase ◽  
Oxide Semiconductor ◽  
Native Oxide ◽  
Semiconductor Surface ◽  
Native Oxide Layer ◽  
Lattice Matching ◽  
Intermediate Phases ◽  
Reaction Thermodynamics ◽  
Polar Low

AbstractA review of the growth of oriented oxides on Si and Ill-V semiconductors provides insight into some of the common themes of oxide/semiconductor epitaxy. The nature and success of the epitaxy can be attributed to four primary factors: (i) semiconductor surface preparation; (ii) oxide/semiconductor reaction thermodynamics; (iii) surface and interfacial polarity; and (iv) structural matching (lattice matching, thermal expansion, and symmetry). Semiconductor surface preparation governs the initial stages of epitaxy for systems such as MgO/GaAs and In2O3/InAs. In these cases, the epitaxial development depends on the presence or absence of a native oxide layer prior to growth. Chemical reaction can also influence the epitaxial process, as is illustrated in the growth of gadolinium oxide on Si. In general, the initial stages of epitaxy reflect a thermodynamic competition between the formation of the desired oxide phase, oxidation of the semiconductor, and formation of intermediate phases such as silicides and silicates. An analysis of possible reactions is presented for selected binary and ternary oxides with Si and GaAs. Surface and interfacial energy can also play an important role in determining the morphology and orientation of oxides having polar low-index faces, as illustrated in the growth of fluorite and related bixbyite oxides such as CeO2, In2O3 and Y2O3. The epitaxial relationships between the oxide and semiconductor may be rationalized in terms of either direct lattice matching or higher order epitaxy.

Experimental Study on 28nm Chip/Package Interactions in eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages

2016 ◽  
Vol 2016 (S2) ◽  
pp. S1-S22
Author(s):  
Dongkai Shangguan ◽  
Yao Jian Lin ◽  
Won Kyung Choi ◽  
Seng Guan Chow ◽  
Seung Wook Yoon
Keyword(s):  
Experimental Study ◽  
Form Factor ◽  
Structural Design ◽  
Heat Dissipation ◽  
Functional Integration ◽  
Thermal Characterization ◽  
Structural Defects ◽  
Wafer Level ◽  
Factors Affecting ◽  
Ball Grid Array Packages

To meet the continued demand for form factor reduction and functional integration of electronic devices, WLP (Wafer Level Packaging) is an attractive packaging solution with many advantages in comparison with standard BGA (Ball Grid Array) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, eWLB (Embedded Wafer Level BGA) is a fan-out WLP solution which can enable applications that require higher I/O density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also facilitates integration of multiple dies vertically and horizontally in a single package without using substrates. For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in eWLB fan-out WLP with multilayer RDL's. Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Warpage, die cracking and other failures were characterized through metrology measurements and electrical tests. Board assembly processes (including SMT, underfill, etc.) were also studied. The influence of materials and structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.

Metal-Bonding-Based Hermetic Wafer-Level MEMS Packaging Technology Using In-Plane Feedthrough

2018 ◽  
Vol 138 (10) ◽  
pp. 485-494
Author(s):  
Masaaki Moriyama ◽  
Yukio Suzuki ◽  
Kentaro Totsu ◽  
Hideki Hirano ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Mems Packaging ◽  
Metal Bonding

Importance of Surface Preparation in Direct Ion Beam Deposition(Ibd)

1989 ◽  
Vol 157 ◽  
Author(s):  
Kiyoshi Miyake
Keyword(s):  
Preparation Method ◽  
Ion Beam ◽  
Surface Preparation ◽  
Hydrogen Ion ◽  
Native Oxide ◽  
Effective Surface ◽  
Ion Beam Deposition ◽  
Gas Contamination ◽  
Major Factors ◽  
Beam Deposition

ABSTRACTFundamental aspects of direct ion beam deposition (IBD) are discussed, stressing surface preparation and contamination problems. Residual gas contamination, ion beam induced metal contamination, and presence of surface native oxide before deposition are shown to be the major factors hindering low temperature epitaxial growth in IBD. A low energy hydrogen ion bombardment is demonstrated as an effective surface preparation method to remove surface native oxide in the case of silicon deposition.

Surface Potential Difference Imaging Applied to Wet Clean Monitoring

2009 ◽  
Vol 145-146 ◽  
pp. 109-112 ◽  
Author(s):  
Adrien Danel ◽  
S. Sage ◽  
M.C. Roure ◽  
D. Peters ◽  
Jeff Hawthorne ◽  
...  
Keyword(s):  
Light Scattering ◽  
Surface Potential ◽  
Surface Preparation ◽  
High Sensitivity ◽  
Potential Difference ◽  
Native Oxide ◽  
Particle Detection ◽  
Patterned Wafers ◽  
Surface Work ◽  
Difference Imaging

The monitoring and optimization of wet clean and surface preparation processes is a major challenge in the microelectronics industry [1, 2]. Today, the main methods used in clean rooms are visual inspection by light scattering (principally applied to particle detection) and metallic contamination detection by Total-reflection X-Ray Fluorescence (TXRF). These methods, despite good sensitivity and recent progress [3, 4] are not sufficient, especially considering non-visual defects not measurable by light scattering, nor TXRF due to their chemical nature or to their size and location (TXRF is not applicable to light elements – with Z < 11 – and is typically a 1 cm resolution tool, with 1 to 2 cm edge exclusion). Non-vibrating Surface Potential Difference Imaging (SPDI), introduced in 2005 under the name of ChemetriQ® is an in-line, non-contact, non-destructive inspection technique based on the imaging of surface Work Function (WF) lateral non-uniformities [5]. Recent studies show very promising results for SPDI: high sensitivity to traces of metals on Si wafers with native oxide [6]; fast imaging capabilities of unpatterned or patterned wafers with sensitivity to chemical residues and charge [7, 8]. In this work, the ChemetriQ method is evaluated for in-line control of wet clean processes. The variation of SPDI data from various contaminants is compared to intra- and inter-wafer variations related to the cleaning and measurement conditions. Note that all wafer maps are presented with the notch oriented at 6:00.

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