Application and Optimization of Automated ECCI Mapping to the Analysis of Lowly Defective Epitaxial Films on Blanket or Patterned Wafers

The physical limits of CMOS scaling, as predicted by Moore's Law, should have already been reached several years ago. However, the scaling of transistors is still ongoing due to continuous improvements in material quality enabling the fabrication of complex device structures with nm-size dimensions. More than ever, the structural properties and the eventual presence of crystalline defects in the various semiconductor materials (SiGe, III/V) play a critical role. Electron channeling contrast imaging (ECCI) is a powerful defect analysis technique developed in recent years. The technique allows for fast and non-destructive characterizations with the potential for extremely low detection limits. The analysis of lowly defective materials requires measurements over large areas to obtain statistically relevant data. Automated ECCI mapping routines enable the quantification of crystalline defect densities as low as ~1e5 cm-2, e.g., Si0.75Ge0.25 strain relaxed buffers (SRB) epitaxially grown on a Si substrate. Methods to reduce the total measurement time without compromising its sensitivity will be discussed. The measurement routine has also been optimized to detect extended crystalline defects in III/V layers, selectively grown on shallow trench isolation patterned Si wafers. Throughout these examples, this study demonstrates the great potential of ECCI as a versatile and industry-relevant technique for defect analysis.

Hybrid CMP Slurry Supply System Using Ionization and Atomization

Chemical mechanical planarization (CMP) is frequently used in semiconductor manufacturing to polish the surfaces of multiple layers in a wafer. The CMP uses a slurry that aids in fabricating a smooth surface by removing the excess materials. However, excessive use of slurry affects the environment and is expensive. Therefore, we propose a hybrid slurry supply system that combines ionization and atomization to reduce slurry consumption and improve the polishing quality. The proposed hybrid system atomizes the ionized slurry using electrolysis and a spray slurry nozzle. We compared the material removal rate (MRR) and polishing uniformity based on the slurry supply systems used in Cu and SiO2 non-patterned wafers. Additionally, the step height reduction and dishing were compared in the Cu-patterned wafers. The experimental analysis using the hybrid system confirmed a 23% and 25% improvement in the MRR and uniformity, respectively, in comparison with the conventional slurry supply system. This improvement can be attributed to the chemical activation and uniform supply of the ionized and atomized slurries, respectively. Moreover, a significant reduction was observed in dishing and pitch-size dependence. Furthermore, the proposed system prevents heat accumulation between the CMP processes, serving as a cooling system.

Copper Catalysis Effect Investigation for TiW Etch Process on Patterned Wafers

The use of various H2O2 based chemistries for TiW etch was studied on single wafer and wet bench tools. The focus of the investigation was put on the different behaviors of these chemicals on blanket and patterned wafers. The results of the etch rate tests showed much higher values on the wafers where copper was exposed, leading to the hypothesis that the etch rate on TiW should be driven by the catalysis effect of the transition metal on the H2O2 decomposition reaction. Additional optical inspections, ToF SIMS, SEM and TEM analyses were carried out to confirm this hypothesis and find the best conditions in terms of morphology for RDL applications. Finally, the collected data were also used to evaluate the process cycle time and cost of ownership.

Automated System for Optical Inspection of Defects in Resist-coated Non-patterned Wafer

Quality control of the resist coating on a silicon wafer is one of the major tasks prior to the exposition of patterns into the resist layer. Thus, the ability to inspect and identify the physical defect in the resist layer plays an important role. The absence of any unwanted defect in resist is an ultimate requirement for preparation of precise and functional micro- or nano-patterned surfaces. Currently used wafer inspection systems are mostly utilized in semiconductor or microelectronic industry to inspect non-patterned or patterned wafers (integrated circuits, photomasks, … etc.) in order to achieve high yield production. Typically, they are based on acoustic micro-imaging, optical imaging or electron microscopy. This paper presents the design of a custom optical-based inspection device for small batch lithography production that allows scanning a wafer surface with an optical camera and by analyzing the captured images to determine the coordinates (X, Y), the size and the type of the defects in the resist layer. In addition, software responsible for driving the scanning device and for advanced image processing is presented. Keywords: Optical inspection, Resist layer, Non-patterned wafer, Quality control.

Novel X-ray Microscopic Chemical Imaging for Rapid Non-Destructive Identification of Structural and Compositional Defects from Microbumps to FinFET

New heterogeneous 3D integration schemes and continuing miniaturization of semiconductor packaging components, such as micropillars, are driving demand for substantive changes to conventional PFA (physical failure analysis). In particular, desired performance capabilities include the ability to nondestructively determine failures within seconds to minutes. New tools should be quantitative, have sufficient resolution to determine sub-micron sized defects and voids in TSVs at the wafer or package level. It should also measure thickness and their material composition of multilayer structures above the wafer surface, such as microbumps, or those below the surface including UBM and RDL. In this paper we are introducing a novel x-ray fluorescence microscope technique capable of solving the above applications in advanced packaging for PFA and process development. The same technique can also be applied in the front end metrology of new gate materials, 3D FinFET structures within test structures in patterned wafers. Characterization of sub nanoscopic changes (sensitivity of sub-angstrom) in film and dopants deposited in 3D structures will also be shown. With its high sensitivity for trace materials, contamination analysis of post hard mask residue, post metal etch residue especially in high aspect ratio structures is also possible.

Metal Removal Efficiency in High Aspect Ratio Structures

An extremely low level of metal contamination is required for specific devices like memories and CMOS Image sensors. Most of past work in the literature has focused on blanket wafer decontamination, since metrology is mostly adapted to flat surfaces. Metal removal efficiency has been compared between blanket wafers versus high aspect ratio deep trenches wafers. Two different metrology technics enable a quantitative and spatial metal removal determination on patterned wafers. Efficient cleaning in high aspect ratio structures requires much longer cleaning recipes than on flat surfaces.