Circuit design of reconfigurable dynamic logic based on double gate CNTFETs focusing on number of states of back gate voltages

Contemporary Engineering Sciences ◽

10.12988/ces.2014.3952 ◽

2014 ◽

Vol 7 ◽

pp. 39-52 ◽

Cited By ~ 1

Author(s):

Junki Kato ◽

Shigeyoshi Watanabe ◽

Hiroshi Ninomiya ◽

Manabu Kobayashi ◽

Yasuyuki Miura

Keyword(s):

Circuit Design ◽

Dynamic Logic ◽

Double Gate ◽

Back Gate

Download Full-text

Circuit design of 2-input reconfigurable dynamic logic based on double gate MOSFETs with whole set of 16 functions

Contemporary Engineering Sciences ◽

10.12988/ces.2014.31061 ◽

2014 ◽

Vol 7 ◽

pp. 87-102 ◽

Cited By ~ 1

Author(s):

Junki Kato ◽

Shigeyoshi Watanabe ◽

Hiroshi Ninomiya ◽

Manabu Kobayashi ◽

Yasuyuki Miura

Keyword(s):

Circuit Design ◽

Dynamic Logic ◽

Double Gate

Download Full-text

Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e96.a.1642 ◽

2013 ◽

Vol E96.A (7) ◽

pp. 1642-1644

Author(s):

Manabu KOBAYASHI ◽

Hiroshi NINOMIYA ◽

Shigeyoshi WATANABE

Keyword(s):

Circuit Design ◽

Double Gate ◽

Reconfigurable Logic

Download Full-text

Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) ◽

10.1145/383082.383136 ◽

2001 ◽

Cited By ~ 7

Author(s):

Rongtian Zhang ◽

Kaushik Roy ◽

David Janes

Keyword(s):

Low Power ◽

Circuit Design ◽

High Performance ◽

Double Gate ◽

Fully Depleted ◽

Nano Scale

Download Full-text

Extremely-scaled double-gate CMOS with non-self-aligned back gate

IEEE VLSI-TSA International Symposium on VLSI Technology 2005 (VLSI-TSA-Tech) VTSA-05 ◽

10.1109/vtsa.2005.1497100 ◽

2005 ◽

Author(s):

Keunwoo Kim ◽

H.I. Hanafi ◽

J. Cai ◽

Ching-Te Chuang

Keyword(s):

Double Gate ◽

Back Gate

Download Full-text

Study of Extended Back Gate Double Gate JunctionLess Transistor: Theoretical and Numerical Investigation

Springer Proceedings in Physics - The Physics of Semiconductor Devices ◽

10.1007/978-3-319-97604-4_98 ◽

2019 ◽

pp. 633-642

Author(s):

Vandana Kumari ◽

Abhineet Sharan ◽

Manoj Saxena ◽

Mridula Gupta

Keyword(s):

Numerical Investigation ◽

Double Gate ◽

Back Gate ◽

Junctionless Transistor

Download Full-text

A Novel Scaling Theory for Effective Conductive Path Effect of Double Gate (DG) MOSFETs for Nano-Scale CMOS Circuit Design

2008 International Conference on Signal Processing, Communications and Networking ◽

10.1109/icscn.2008.4447218 ◽

2008 ◽

Author(s):

N. B. Balamurugan ◽

K. Sankaranarayanan ◽

V Priyadharsini ◽

M. Ishwarya Devi

Keyword(s):

Circuit Design ◽

Scaling Theory ◽

Double Gate ◽

Cmos Circuit ◽

Conductive Path ◽

Nano Scale

Download Full-text

Circuit design of 2-input reconfigurable dynamic logic based on stacked type Fe-FET with whole set of 16 functions

Contemporary Engineering Sciences ◽

10.12988/ces.2017.79126 ◽

2017 ◽

Vol 10 ◽

pp. 1133-1142

Author(s):

Tomohiro Yokota ◽

Shigeyoshi Watanabe

Keyword(s):

Circuit Design ◽

Dynamic Logic

Download Full-text

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

Solid-State Electronics ◽

10.1016/j.sse.2008.06.051 ◽

2008 ◽

Vol 52 (12) ◽

pp. 1895-1903 ◽

Cited By ~ 7

Author(s):

Abhinav Kranti ◽

G. Alastair Armstrong

Keyword(s):

Low Voltage ◽

Double Gate ◽

Back Gate ◽

Rf Applications

Download Full-text

Diminished Short Channel Effects in Nanoscale Double-Gate Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect-Transistors due to Induced Back-Gate Step Potential

Japanese Journal of Applied Physics ◽

10.1143/jjap.44.6508 ◽

2005 ◽

Vol 44 (9A) ◽

pp. 6508-6509 ◽

Cited By ~ 16

Author(s):

M. Jagadesh Kumar ◽

G. Venkateshwar Reddy

Keyword(s):

Field Effect Transistors ◽

Metal Oxide Semiconductor ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Double Gate ◽

Short Channel Effects ◽

Short Channel ◽

Step Potential ◽

Back Gate ◽

Channel Effects

Download Full-text

DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS

2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502) ◽

10.1109/sispad.2000.871229 ◽

2002 ◽

Cited By ~ 10

Author(s):

MeiKei Ieong ◽

H.-S.P. Wong ◽

Yuan Taur ◽

P. Oldiges ◽

D. Frank

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Back Gate

Download Full-text