Circuit design of 2-input reconfigurable dynamic logic based on stacked type Fe-FET with whole set of 16 functions

2017 ◽  
Vol 10 ◽  
pp. 1133-1142
Author(s):  
Tomohiro Yokota ◽  
Shigeyoshi Watanabe
Keyword(s):  
Circuit Design ◽  
Dynamic Logic

Circuit design of reconfigurable dynamic logic based on double gate CNTFETs focusing on number of states of back gate voltages

2014 ◽  
Vol 7 ◽  
pp. 39-52 ◽  
Author(s):  
Junki Kato ◽  
Shigeyoshi Watanabe ◽  
Hiroshi Ninomiya ◽  
Manabu Kobayashi ◽  
Yasuyuki Miura
Keyword(s):  
Circuit Design ◽  
Dynamic Logic ◽  
Double Gate ◽  
Back Gate

Low power dynamic logic circuit design using a pseudo dynamic buffer

Integration ◽  
2012 ◽  
Vol 45 (4) ◽  
pp. 395-404 ◽  
Author(s):  
Fang Tang ◽  
Amine Bermak ◽  
Zhouye Gu
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Dynamic Logic ◽  
Logic Circuit ◽  
Power Dynamic

Circuit design of 2-input reconfigurable dynamic logic based on double gate MOSFETs with whole set of 16 functions

2014 ◽  
Vol 7 ◽  
pp. 87-102 ◽  
Author(s):  
Junki Kato ◽  
Shigeyoshi Watanabe ◽  
Hiroshi Ninomiya ◽  
Manabu Kobayashi ◽  
Yasuyuki Miura
Keyword(s):  
Circuit Design ◽  
Dynamic Logic ◽  
Double Gate

scholarly journals Research on High Speed Low Power Digital Logic Family for Pipelined Arithmatic Logic Structures

2019 ◽  
Vol 8 (12S) ◽  
pp. 637-648
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
High Speed ◽  
Dynamic Logic ◽  
Structure Design ◽  
Clock Speed ◽  
Design Structure ◽  
Dynamic Structures ◽  
Logic Structures ◽  
Data Length

The bit size of the data length process depends on the clock speed operation .the clock speed increases with the bit size of the data length .but this increases deal in the circuit to overcome this pipeline and parallel processing is used. This will increase the performance of the circuit with the advancement of the high speed technology the data length process per clock is increasing rapidly from Intel 1 intel20 to Intel series. Adder is an important adder structure design which uses parallel and pipelining scheme are RCA and SFA. To design these adders we need high speed processing digital electronic circuit which must be high speed and low power. There are various types of logic families which we are discuss in this paper. From static to dynamic circuit design why dynamic is faster than static. and various types of dynamic circuit design structure this paper basically focus on constant delay logic style and why it is superior to other dynamic structures such as domino logic ,dynamic logic np CMOS logic,C2MOS logic ,NORA CMOS logic design, Zipper CMOS,FTL logic.

Limited switch dynamic logic circuits for high-speed low-power circuit design

2006 ◽  
Vol 50 (2.3) ◽  
pp. 277-286 ◽  
Author(s):  
W. Belluomini ◽  
D. Jamsek ◽  
A. K. Martin ◽  
C. McDowell ◽  
R. K. Montoye ◽  
...  
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
High Speed ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
Power Circuit
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