scholarly journals Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design

2001 ◽  
Author(s):  
Rongtian Zhang ◽  
Kaushik Roy ◽  
David Janes
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
High Performance ◽  
Double Gate ◽  
Fully Depleted ◽  
Nano Scale

Planar fully depleted SOI technology: The convergence of high performance and low power towards multimedia mobile applications

2012 ◽  
Author(s):  
Bertrand Pelloux-Prayer ◽  
Milovan Blagojevic ◽  
Olivier Thomas ◽  
Amara Amara ◽  
Andrei Vladimirescu ◽  
...  
Keyword(s):  
Low Power ◽  
Mobile Applications ◽  
High Performance ◽  
Fully Depleted ◽  
Soi Technology

Use of nano-scale double-gate MOSFETs in low-power tunable current mode analog circuits

2008 ◽  
Vol 54 (3) ◽  
pp. 211-217 ◽  
Author(s):  
Hesham F. A. Hamed ◽  
Savas Kaya ◽  
Janusz A. Starzyk
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Current Mode ◽  
Double Gate ◽  
Nano Scale

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

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