scholarly journals Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

2013 ◽  
Vol 2013 ◽  
pp. 1-24
Author(s):  
Emna Amouri ◽  
Habib Mehrez ◽  
Zied Marrakchi
Keyword(s):  
Routing Algorithm ◽  
Wire Length ◽  
Wave Dynamic ◽  
Placement And Routing ◽  
Power Attacks ◽  
Differential Pair ◽  
Routing Techniques ◽  
Mesh Architecture

The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-railsignals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree-based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number.

Pathfinder Algorithm Modification for CPLD and FPGA Routing Stage

2021 ◽  
Vol 26 (5) ◽  
pp. 399-409
Author(s):  
M.A. Zapletina ◽  
◽  
S.V. Gavrilov ◽  
◽  
Keyword(s):  
Computer Aided Design ◽  
Digital Circuits ◽  
Routing Algorithm ◽  
Design Flow ◽  
Negative Effect ◽  
Industrial Projects ◽  
Placement And Routing ◽  
Aided Design ◽  
The Impact

One of the main advantages of FPGA and CPLD is the high development speed; therefore, the importance of effective computer-aided design tools for modern microcircuits of these classes cannot be overestimated. Placement and routing are the most time-consuming stages of FPGA/CPLD design flow. The quality of results of these stages is crucial to the final perfor-mance of custom digital circuits implemented on FPGA/CPLD. The paper discusses an approach to accelerating the routing stage within the layout synthesis flow for FPGA/CPLD by introducing a few algorithmic improvements to a routing procedure. The basic routing algorithm under study is a modified Pathfinder for a mixed routing resource graph. Pathfinder is a well-known negotiation-based routing algorithm that works on the principle of iteratively eliminating congestions of chip routing resources. For experiments, the sets of test digital circuits ISCAS'85, ISCAS'89, LGSynth'89 and several custom industrial projects were used. The impact of the proposed algorithmic improvements was analyzed using four FPGA/CPLD architectures. It has been established that due to the improvements of the algorithm proposed in the paper, the average reduction in routing time was from 1.3 to 2.6 times, depending on the FPGA/CPLD architecture, with no significant negative effect on the timing characteristics of the designed circuits.

Design of High Speed Reconfigurable Distributed Life Time Efficient Routing Algorithm in Wireless Sensor Network

2020 ◽  
Vol 17 (9) ◽  
pp. 3860-3866
Author(s):  
M. L. Umashankar ◽  
S. Mallikarjunaswamy ◽  
M. V. Ramakrishna
Keyword(s):  
Shortest Path ◽  
High Speed ◽  
Routing Algorithm ◽  
Shortest Paths ◽  
Life Time ◽  
Wireless Sensor ◽  
Signal Interference ◽  
Energy Efficient Routing ◽  
Shortest Path Routing ◽  
Routing Techniques

Designing an energy-efficient routing makes the Wireless Sensor Networks (WSN) more effective and attractive for different applications. The WSN communication system power consumption mainly depends on three aspects such as routing cost computation, signal interference, and routing distance. All three factors are equally important in order to improve the network performance. The system reliability and deployment cost depends on the energy efficiency of the WSN. The energy related cost assignment and shortest paths identification are used in existing routing techniques. In the existing routing techniques maximum achievable lifetime and optimal link cost are low. Hence greatest possible performance can be achieved in distributed routing algorithm by finding shortest path. Maximum lifetime and best cost link can be generally obtained using distributed shortest path routing algorithm. In this paper high speed reconfigurable distributed Lifetime-Efficient Routing algorithm is designed to provide route selection outline with low complexity and obtain better performance compared to existing routing algorithm.

A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs

2008 ◽  
Vol 4 (3) ◽  
pp. 275-289 ◽  
Author(s):  
Kostas Siozios ◽  
Dimitrios Soudris
Keyword(s):  
Routing Algorithm ◽  
Placement And Routing

scholarly journals An Integrated Perspective of Crucial Research Issues in NoC Router Design

2020 ◽  
Vol 9 (1) ◽  
pp. 480-484
Keyword(s):  
High Throughput ◽  
Routing Algorithm ◽  
Round Robin ◽  
Research Issues ◽  
Overall Performance ◽  
Mesh Architecture

A new reliable high throughput NOC router design is proposed with FSM based smart arbiter module for 4X4 Mesh architecture. This design is based the XY routing algorithm with prioritized round robin arbitration and synthesis of the proposed design is done on Spartan III FPGA. An enhanced work is also done in this paper to explore the drawbacks of the exceptional techniques of the existing generation and to research the scope for overall performance improvisation of the NoC designing

scholarly journals Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

VLSI Design ◽  
1999 ◽  
Vol 10 (1) ◽  
pp. 1-20 ◽  
Author(s):  
Dirk Stroobandt ◽  
Jan Van Campenhout
Keyword(s):  
Upper Bound ◽  
Accurate Estimate ◽  
Optimal Placement ◽  
Electronic Circuits ◽  
Length Estimation ◽  
Design Cycle ◽  
Placement And Routing ◽  
Routing Techniques ◽  
Space Requirements

Important layout properties of electronic circuits include space requirements and interconnection lengths. In the process of designing these circuits, a reliable pre-layout interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally observed average lengths. Yet, this upper bound deviates from the experimental value by a factor δ ≈ 2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.

scholarly journals Speeding Up FPGA Placement via Partitioning and Multithreading

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Cristinel Ababei
Keyword(s):  
Routing Algorithms ◽  
Design Flow ◽  
Wire Length ◽  
Fpga Design ◽  
Circuit Delay ◽  
Hybrid Parallelization ◽  
Multiple Cores ◽  
Fpga Placement ◽  
Placement And Routing ◽  
Placement Algorithm

One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region-based partitioning and multithreading. In the first step of this approach placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of2.5×using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.

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