Macro and Micro Architectures for Network on Chip

Network on chip (NoC) paradigm replaces traditional, dedicated, and proprietary bus architectures of system on chip (SoC), and it is widely accepted by the system-level designers. In this chapter, an overview of the NoC design is presented in two different dimensions called macro-architectures and micro-architectures based on the design perspectives. Macro-architectures adopt the concept of computer network along with new innovations in topologies, protocols, and routing algorithms and so on whereas micro-architectures involve in the development of schedulers, arbiters, routers, and network adapter with existing or new concepts. From the comparison result, most of the NoC prototypes are developed with 2-D mesh architecture with packed switched concept. Apart from mesh architectures, some of the complex and hybrid concepts are also developed and discussed in this chapter.

An Integrated Perspective of Crucial Research Issues in NoC Router Design

A new reliable high throughput NOC router design is proposed with FSM based smart arbiter module for 4X4 Mesh architecture. This design is based the XY routing algorithm with prioritized round robin arbitration and synthesis of the proposed design is done on Spartan III FPGA. An enhanced work is also done in this paper to explore the drawbacks of the exceptional techniques of the existing generation and to research the scope for overall performance improvisation of the NoC designing

Fast Parallel Algorithm for Prefix Computation in Multi-Mesh Architecture

A parallel algorithm for prefix computation on [Formula: see text] data elements mapped on a Multi Mesh (MM) network of [Formula: see text] processing elements is presented here. The time required by the proposed algorithm is significantly less than that by any of the existing algorithms for prefix computation on mesh-like architectures due to the specific interconnection pattern used in the MM network. The proposed technique requires [Formula: see text] time for data communication and [Formula: see text] time for computation, when mapped on a MM network constituted by [Formula: see text] meshes, each of size [Formula: see text]. The data communication time in the proposed algorithm is less than the prefix sum algorithm proposed in extended Multi Mesh. To be precise, instead of [Formula: see text] communication time the proposed algorithm requires a data communication time of [Formula: see text] only. Moreover, the proposed parallel algorithm does not need any extra inter block links as used in the extended Multi Mesh.