scholarly journals Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

VLSI Design ◽  
1999 ◽  
Vol 10 (1) ◽  
pp. 1-20 ◽  
Author(s):  
Dirk Stroobandt ◽  
Jan Van Campenhout
Keyword(s):  
Upper Bound ◽  
Accurate Estimate ◽  
Optimal Placement ◽  
Electronic Circuits ◽  
Length Estimation ◽  
Design Cycle ◽  
Placement And Routing ◽  
Routing Techniques ◽  
Space Requirements

Important layout properties of electronic circuits include space requirements and interconnection lengths. In the process of designing these circuits, a reliable pre-layout interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally observed average lengths. Yet, this upper bound deviates from the experimental value by a factor δ ≈ 2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.

Research of Chip Placement and Routing Algorithms for Board-Level Photoelectric Interconnection

2014 ◽  
Vol 556-562 ◽  
pp. 1577-1579
Author(s):  
Jian Liu ◽  
Zhao Hua Wu
Keyword(s):  
Genetic Algorithm ◽  
Genetic Algorithms ◽  
Routing Algorithms ◽  
Optimal Placement ◽  
Improved Method ◽  
Improved Genetic Algorithm ◽  
C Language ◽  
Placement And Routing ◽  
Board Level ◽  
Improved Algorithm

This document improved genetic algorithm and Intelligent discern points algorithmin chip placement and routing for Board-level photoelectric interconnection, by comparisonofthe algorithm results to verify the effectiveness and practicality of the improved algorithm. First introduced the features of chip placement and routing for Board-level Photoelectric Interconnection. Then describes the improved method of genetic algorithms and intelligent discern points algorithms. Finally, implement algorithm by C language on VC6.0++ platform, while the data import MATLAB to displays the optimal placement and routing results. The results show that the effectiveness of improved algorithm, which has a guiding significance for the chip placement and routing.

scholarly journals Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

2013 ◽  
Vol 2013 ◽  
pp. 1-24
Author(s):  
Emna Amouri ◽  
Habib Mehrez ◽  
Zied Marrakchi
Keyword(s):  
Routing Algorithm ◽  
Wire Length ◽  
Wave Dynamic ◽  
Placement And Routing ◽  
Power Attacks ◽  
Differential Pair ◽  
Routing Techniques ◽  
Mesh Architecture

The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-railsignals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree-based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number.

scholarly journals Programmatic implications of implementing the relational algebraic capacitated location (RACL) algorithm outcomes on the allocation of laboratory sites, test volumes, platform distribution and space requirements

2017 ◽  
Vol 6 (1) ◽  
Author(s):  
Naseem Cassim ◽  
Honora Smith ◽  
Lindi M. Coetzee ◽  
Deborah K. Glencross
Keyword(s):  
Point Of Care ◽  
Fold Increase ◽  
Optimal Placement ◽  
Local Conditions ◽  
Laboratory Service ◽  
Space Requirements ◽  
The Impact ◽  
Capacitated Location ◽  
Objective Methodology ◽  
Cd4 Testing

Introduction: CD4 testing in South Africa is based on an integrated tiered service delivery model that matches testing demand with capacity. The National Health Laboratory Service has predominantly implemented laboratory-based CD4 testing. Coverage gaps, over-/under-capacitation and optimal placement of point-of-care (POC) testing sites need investigation.Objectives: We assessed the impact of relational algebraic capacitated location (RACL) algorithm outcomes on the allocation of laboratory and POC testing sites.Methods: The RACL algorithm was developed to allocate laboratories and POC sites to ensure coverage using a set coverage approach for a defined travel time (T). The algorithm was repeated for three scenarios (A: T = 4; B: T = 3; C: T = 2 hours). Drive times for a representative sample of health facility clusters were used to approximate T. Outcomes included allocation of testing sites, Euclidian distances and test volumes. Additional analysis included platform distribution and space requirement assessment. Scenarios were reported as fusion table maps.Results: Scenario A would offer a fully-centralised approach with 15 CD4 laboratories without any POC testing. A significant increase in volumes would result in a four-fold increase at busier laboratories. CD4 laboratories would increase to 41 in scenario B and 61 in scenario C. POC testing would be offered at two sites in scenario B and 20 sites in scenario C.Conclusion: The RACL algorithm provides an objective methodology to address coverage gaps through the allocation of CD4 laboratories and POC sites for a given T. The algorithm outcomes need to be assessed in the context of local conditions.

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