scholarly journals IPR: An Integrated Placement and Routing Algorithm

2007 ◽  
Author(s):  
Min Pan ◽  
Chris Chu
Keyword(s):  
Routing Algorithm ◽  
Integrated Placement ◽  
Placement And Routing

Pathfinder Algorithm Modification for CPLD and FPGA Routing Stage

2021 ◽  
Vol 26 (5) ◽  
pp. 399-409
Author(s):  
M.A. Zapletina ◽  
◽  
S.V. Gavrilov ◽  
◽  
Keyword(s):  
Computer Aided Design ◽  
Digital Circuits ◽  
Routing Algorithm ◽  
Design Flow ◽  
Negative Effect ◽  
Industrial Projects ◽  
Placement And Routing ◽  
Aided Design ◽  
The Impact

One of the main advantages of FPGA and CPLD is the high development speed; therefore, the importance of effective computer-aided design tools for modern microcircuits of these classes cannot be overestimated. Placement and routing are the most time-consuming stages of FPGA/CPLD design flow. The quality of results of these stages is crucial to the final perfor-mance of custom digital circuits implemented on FPGA/CPLD. The paper discusses an approach to accelerating the routing stage within the layout synthesis flow for FPGA/CPLD by introducing a few algorithmic improvements to a routing procedure. The basic routing algorithm under study is a modified Pathfinder for a mixed routing resource graph. Pathfinder is a well-known negotiation-based routing algorithm that works on the principle of iteratively eliminating congestions of chip routing resources. For experiments, the sets of test digital circuits ISCAS'85, ISCAS'89, LGSynth'89 and several custom industrial projects were used. The impact of the proposed algorithmic improvements was analyzed using four FPGA/CPLD architectures. It has been established that due to the improvements of the algorithm proposed in the paper, the average reduction in routing time was from 1.3 to 2.6 times, depending on the FPGA/CPLD architecture, with no significant negative effect on the timing characteristics of the designed circuits.

A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs

2008 ◽  
Vol 4 (3) ◽  
pp. 275-289 ◽  
Author(s):  
Kostas Siozios ◽  
Dimitrios Soudris
Keyword(s):  
Routing Algorithm ◽  
Placement And Routing

scholarly journals Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

2013 ◽  
Vol 2013 ◽  
pp. 1-24
Author(s):  
Emna Amouri ◽  
Habib Mehrez ◽  
Zied Marrakchi
Keyword(s):  
Routing Algorithm ◽  
Wire Length ◽  
Wave Dynamic ◽  
Placement And Routing ◽  
Power Attacks ◽  
Differential Pair ◽  
Routing Techniques ◽  
Mesh Architecture

The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-railsignals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree-based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number.

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