High Density Copper Bump Technology Integrated With Wafer Level Package

Xiang Zeng; Patty Chang-Chien; Chi Cheung; G Akerling; Rosie Johnson; T. Chung; Kelly Hennig

doi:10.1149/1.2983154

High Density Copper Bump Technology Integrated With Wafer Level Package

ECS Transactions ◽

10.1149/1.2983154 ◽

2019 ◽

Vol 16 (7) ◽

pp. 15-21 ◽

Cited By ~ 2

Author(s):

Xiang Zeng ◽

Patty Chang-Chien ◽

Chi Cheung ◽

G Akerling ◽

Rosie Johnson ◽

...

Keyword(s):

High Density ◽

Wafer Level ◽

Wafer Level Package

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Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications

2016 IEEE 66th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2016.203 ◽

2016 ◽

Cited By ~ 45

Author(s):

Vempati Srinivasa Rao ◽

Chai Tai Chong ◽

David Ho ◽

Ding Mian Zhi ◽

Chong Ser Choong ◽

...

Keyword(s):

Mobile Applications ◽

High Density ◽

Wafer Level ◽

Fine Pitch ◽

Wafer Level Package

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Development of Chip-to-Wafer (C2W) bonding process for high density I/Os Fan-Out Wafer Level Package (FOWLP)

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC) ◽

10.1109/eptc.2016.7861516 ◽

2016 ◽

Cited By ~ 1

Author(s):

Sharon Pei-Siang Lim ◽

Ser Choong Chong ◽

Mian Zhi Ding ◽

Vempati Srinivasa Rao

Keyword(s):

Bonding Process ◽

High Density ◽

Wafer Level ◽

Wafer Level Package

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High Density Copper Bump Technology Integrated With Wafer Level Package

ECS Meeting Abstracts ◽

10.1149/ma2008-02/34/2234 ◽

2008 ◽

Keyword(s):

High Density ◽

Wafer Level ◽

Wafer Level Package

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Design and Development of High Density Fan-Out Wafer Level Package (HD-FOWLP) for Deep Neural Network (DNN) Chiplet Accelerators using Advanced Interface Bus (AIB)

2021 IEEE 71st Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc32696.2021.00204 ◽

2021 ◽

Author(s):

Mihai D. Rotaru ◽

Wei Tang ◽

Dutta Rahul ◽

Zhengya Zhang

Keyword(s):

Neural Network ◽

Deep Neural Network ◽

High Density ◽

Wafer Level ◽

Design And Development ◽

Wafer Level Package

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HIGH DENSITY AND HIGH BANDWIDTH CHIP-TO-CHIP CONNECTIONS WITH 20μm PITCH FLIP-CHIP ON FAN-OUT WAFER LEVEL PACKAGE

2018 International Wafer Level Packaging Conference (IWLPC) ◽

10.23919/iwlpc.2018.8573262 ◽

2018 ◽

Cited By ~ 1

Author(s):

Podpod ◽

E. Beyne ◽

D. Velenis ◽

A. Phommahaxay ◽

P. Bex ◽

...

Keyword(s):

Flip Chip ◽

High Density ◽

Wafer Level ◽

High Bandwidth ◽

Wafer Level Package

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Fabrication of fine patterned structure for high-density Fan-Out Wafer Level Package using dry etching technology

2020 21st International Conference on Electronic Packaging Technology (ICEPT) ◽

10.1109/icept50128.2020.9202525 ◽

2020 ◽

Author(s):

Daisuke Hironiwa ◽

Chao Zuo ◽

Yao-Chih Hsieh ◽

Taichi Suzuki ◽

Yasuhiro Morikawa ◽

...

Keyword(s):

Dry Etching ◽

High Density ◽

Wafer Level ◽

Wafer Level Package

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Drop impact reliability study of high density fan-out wafer level package

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC) ◽

10.1109/eptc.2016.7861586 ◽

2016 ◽

Cited By ~ 2

Author(s):

Zhaohui Chen ◽

Faxing Che ◽

Mian Zhi Ding ◽

David Soon Wee Ho ◽

Tai Chong Chai ◽

...

Keyword(s):

Drop Impact ◽

High Density ◽

Wafer Level ◽

Reliability Study ◽

Impact Reliability ◽

Wafer Level Package

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A Novel Photosensitive Dry-Film Dielectric Material for High Density Package Substrate, Interposer and Wafer Level Package

2016 IEEE 66th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2016.183 ◽

2016 ◽

Cited By ~ 4

Author(s):

Xiaozhu Wei ◽

Yoko Shibasaki

Keyword(s):

Dielectric Material ◽

High Density ◽

Wafer Level ◽

Film Dielectric ◽

Wafer Level Package ◽

Dry Film

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Polyimide Fine-via Etching and Low-damage Surface-modification Process For High-density Fan-out Wafer Level Package

2020 IEEE 70th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc32862.2020.00147 ◽

2020 ◽

Author(s):

Yasuhiro Morikawa ◽

Daisuke Hironiwa ◽

Takahide Murayama

Keyword(s):

Surface Modification ◽

High Density ◽

Wafer Level ◽

Modification Process ◽

Wafer Level Package

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Molding process development for high density I/Os Fan-Out Wafer Level Package (FOWLP) with fine pitch RDL

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC) ◽

10.1109/eptc.2016.7861433 ◽

2016 ◽

Cited By ~ 1

Author(s):

Mian Zhi Ding ◽

Ser Choong Chong ◽

David Soon Wee Ho ◽

Sharon Pei Siang Lim

Keyword(s):

Process Development ◽

High Density ◽

Wafer Level ◽

Molding Process ◽

Fine Pitch ◽

Wafer Level Package

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