Molding process development for high density I/Os Fan-Out Wafer Level Package (FOWLP) with fine pitch RDL

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC) ◽

10.1109/eptc.2016.7861433 ◽

2016 ◽

Cited By ~ 1

Author(s):

Mian Zhi Ding ◽

Ser Choong Chong ◽

David Soon Wee Ho ◽

Sharon Pei Siang Lim

Keyword(s):

Process Development ◽

High Density ◽

Wafer Level ◽

Molding Process ◽

Fine Pitch ◽

Wafer Level Package

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Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications

2016 IEEE 66th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2016.203 ◽

2016 ◽

Cited By ~ 45

Author(s):

Vempati Srinivasa Rao ◽

Chai Tai Chong ◽

David Ho ◽

Ding Mian Zhi ◽

Chong Ser Choong ◽

...

Keyword(s):

Mobile Applications ◽

High Density ◽

Wafer Level ◽

Fine Pitch ◽

Wafer Level Package

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Process development of moldable underfill on fine pitch RDL 1st fan-out wafer level package

2017 IEEE 19th Electronics Packaging Technology Conference (EPTC) ◽

10.1109/eptc.2017.8277547 ◽

2017 ◽

Author(s):

Simon Siak Boon Lim ◽

Mian Zhi Ding ◽

Ser Choong Chong

Keyword(s):

Process Development ◽

Wafer Level ◽

Fine Pitch ◽

Wafer Level Package

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Process Development of Ultra-Fine Pitch High Density Micro Bumps

2018 19th International Conference on Electronic Packaging Technology (ICEPT) ◽

10.1109/icept.2018.8480629 ◽

2018 ◽

Author(s):

Dengfeng Yang ◽

Fengwei Dai ◽

Wenqi Zhang ◽

Guojun Wang ◽

Liqiang Cao

Keyword(s):

Process Development ◽

High Density ◽

Fine Pitch

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Simulation of fatigue life of solder ball joints of an ultra-fine-pitch wafer level package

Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003) ◽

10.1109/eptc.2003.1271606 ◽

2004 ◽

Cited By ~ 7

Author(s):

B. Zhao ◽

A.A. Tay

Keyword(s):

Fatigue Life ◽

Solder Ball ◽

Wafer Level ◽

Fine Pitch ◽

Ball Joints ◽

Wafer Level Package

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Package & board level reliability study of 0.35mm fine pitch wafer level package

2017 18th International Conference on Electronic Packaging Technology (ICEPT) ◽

10.1109/icept.2017.8046464 ◽

2017 ◽

Cited By ~ 1

Author(s):

Peng Sun ◽

Jun Liu ◽

Cheng Xu ◽

Liqiang Cao

Keyword(s):

Wafer Level ◽

Reliability Study ◽

Fine Pitch ◽

Board Level ◽

Wafer Level Package ◽

Board Level Reliability

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Fatigue life estimation of a stretched-solder-column ultra-fine-pitch wafer level package using the macro-micro modelling approach

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546) ◽

10.1109/ectc.2004.1320327 ◽

2004 ◽

Cited By ~ 4

Author(s):

A.C. Chng ◽

A.A.O. Tay ◽

K.M. Lim ◽

E.H. Wong

Keyword(s):

Fatigue Life ◽

Wafer Level ◽

Life Estimation ◽

Fine Pitch ◽

Fatigue Life Estimation ◽

Wafer Level Package ◽

Modelling Approach

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Process development of a new TGV interposer for wafer level package of inertial MEMS device

2016 17th International Conference on Electronic Packaging Technology (ICEPT) ◽

10.1109/icept.2016.7583292 ◽

2016 ◽

Author(s):

Shenglin Ma ◽

Kuili Ren ◽

Yanming Xia ◽

Jun Yan ◽

Rongfeng Luo ◽

...

Keyword(s):

Process Development ◽

Wafer Level ◽

Mems Device ◽

Wafer Level Package

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Circuit Model of Elastomer Probe for Fine Pitch Wafer Level Package Test Applications

2005 7th Electronic Packaging Technology Conference ◽

10.1109/eptc.2005.1614390 ◽

2006 ◽

Author(s):

J. Jayabalan ◽

B.L. Ooi ◽

M.S. Leong ◽

M.K. Iyer

Keyword(s):

Circuit Model ◽

Wafer Level ◽

Fine Pitch ◽

Wafer Level Package

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Development of Chip-to-Wafer (C2W) bonding process for high density I/Os Fan-Out Wafer Level Package (FOWLP)

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC) ◽

10.1109/eptc.2016.7861516 ◽

2016 ◽

Cited By ~ 1

Author(s):

Sharon Pei-Siang Lim ◽

Ser Choong Chong ◽

Mian Zhi Ding ◽

Vempati Srinivasa Rao

Keyword(s):

Bonding Process ◽

High Density ◽

Wafer Level ◽

Wafer Level Package

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Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)

Transactions of The Japan Institute of Electronics Packaging ◽

10.5104/jiepeng.5.122 ◽

2012 ◽

Vol 5 (1) ◽

pp. 122-131 ◽

Cited By ~ 4

Author(s):

Yoshimi Takahashi ◽

Rajiv Dunne ◽

Masazumi Amagai ◽

Yohei Koto ◽

Shoichi Iriguchi ◽

...

Keyword(s):

Process Development ◽

Wafer Level ◽

Molding Process ◽

Through Silicon Vias ◽

Chip Scale Package ◽

Silicon Vias

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