SC1 Cleaning Effect on Electrical Characteristics of 256 Mbit Mobile DRAM with Dual Gate Oxide

2004 ◽  
Vol 151 (10) ◽  
pp. G683 ◽  
Author(s):  
Chihoon Lee ◽  
Namhyuk Jo ◽  
Chanseong Hwang ◽  
Hyeong Joon Kim ◽  
Wonshik Lee
Author(s):  
Cheng-Piao Lin ◽  
Chin-Hsin Tang ◽  
Cheng-Hsu Wu ◽  
Cheng-Chun Ting

Abstract This paper analyzes several SRAM failures using nano-probing technique. Three SRAM single bit failures with different kinds of Gox breakdown defects analyzed are gross function single bit failure, data retention single bit failure, and special data retention single bit failure. The electrical characteristics of discrete 6T-SRAM cells with soft breakdown are discussed and correlated to evidences obtained from physical analysis. The paper also verifies many previously published simulation data. It utilizes a 6T-SRAM vehicle consisting of a large number of SRAM cells fabricated by deep sub-micron, dual gate, and copper metallization processes. The data obtained from this paper indicates that Gox breakdown location within NMOS pull-down device has larger a impact on SRAM stability than magnitude of gate leakage current, which agrees with previously published simulation data.


1997 ◽  
Vol 471 ◽  
Author(s):  
C. M. Park ◽  
J.-H. Jeon ◽  
J.-S. Yoo ◽  
M.-K. Han

ABSTARCT:We have fabricated a new multi-channel polycrystalline silicon thin film transistor (ploy-Si TFT), of which structure may be more effectively hydrogenated than conventional multi-channel poly-Si TFT. The new multi-channel TFT has stripe-cuts in gate electrode so that more hydrogen radicals penetrate into the gate oxide and passivate the active poly-Si layer. After 90 min. hydrogenation of the new device, the electrical characteristics such as threshold voltage and field effect mobility are improved more than those of conventional device.The new multi-channel poly-Si TFT, which receives more hydrogen radicals thorough gate oxide than the conventional multi-channel TFT, can be hydrogenated effectively in long channel devices. Besides the improvement of the device characteristics, our experimental results show that the dominant hydrogenation path is the diffusion though the gate oxide.


2013 ◽  
Vol 740-742 ◽  
pp. 938-941
Author(s):  
Florian Chevalier ◽  
P. Brosselard ◽  
D. Tournier ◽  
G. Grosset ◽  
L. Dupuy ◽  
...  

This paper presents the methodology for the design of a novel 4H-SiC JFET structure able to sustain 3.3 kV. Comparisons between simulation and characterization res will be made. Taken into account the process limitation, we will also discuss the critical steps and their impact on the electrical characteristics. A design methodology based on Baliga's criterion is proposed to obtain the optimal structure. A 50 nm thick thermal oxide grown above vertical channel and the use of a buried p+ layer as second gate electrode are brand new in front of what is found in literature.


2017 ◽  
Vol 64 (3) ◽  
pp. 960-968 ◽  
Author(s):  
Sanjay Kumar ◽  
Ekta Goel ◽  
Kunal Singh ◽  
Balraj Singh ◽  
Prince Kumar Singh ◽  
...  

Author(s):  
Santosh Sharma ◽  
Theodore Letavic ◽  
Yun Shi ◽  
Alain Loiseau ◽  
John-Ellis Monaghan ◽  
...  

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