Electrical Characterization of Ultra-Thin Silicon-On-Insulator Substrates: Static and Split C-V Measurements in the Pseudo-MOSFET Configuration

2013 ◽  
Vol 54 (1) ◽  
pp. 203-208 ◽  
Author(s):  
L. Pirro ◽  
A. Diab ◽  
I. Ionica ◽  
G. Ghibaudo ◽  
S. Cristoloveanu
Keyword(s):  
Electrical Characterization ◽  
Silicon On Insulator ◽  
Thin Silicon

Multi-Scale Thickness and Roughness Characterization of Thin Silicon-On-Insulator Films

2013 ◽  
Vol 2 (9) ◽  
pp. P357-P361 ◽  
Author(s):  
Pablo E. Acosta-Alba ◽  
Oleg Kononchuk ◽  
Grégory Riou ◽  
Cécile Moulin ◽  
Christelle Bertrand-Giuliani ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Scale Thickness ◽  
Multi Scale ◽  
Thin Silicon

Contactless Method for Electrical Characterization of Silicon-on-Insulator Materials

2001 ◽  
Vol 40 (Part 1, No. 9A) ◽  
pp. 5217-5220 ◽  
Author(s):  
Tsugunori Okumura ◽  
Kazuyoshi Eguchi ◽  
Aimin En ◽  
Michihiko Suhara
Keyword(s):  
Electrical Characterization ◽  
Silicon On Insulator ◽  
Contactless Method

Structural, optical and electrical characterization of porous silicon prepared on thin silicon epitaxial layer

2009 ◽  
Vol 924-926 ◽  
pp. 285-290 ◽  
Author(s):  
M. Balarin ◽  
O. Gamulin ◽  
M. Ivanda ◽  
M. Kosović ◽  
D. Ristić ◽  
...  
Keyword(s):  
Porous Silicon ◽  
Epitaxial Layer ◽  
Electrical Characterization ◽  
Silicon Epitaxial Layer ◽  
Thin Silicon

Scanning Capacitance Microscopy for Failure Analysis of SOI-Based Advanced Microprocessors

2010 ◽  
Author(s):  
Lim Soon Huat ◽  
Lwin Hnin-Ei ◽  
Vinod Narang ◽  
J.M. Chin
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
Large Area ◽  
Scanning Capacitance Microscopy ◽  
Electrical Failure ◽  
Silicon Transistors ◽  
Soi Substrates ◽  
Electrical Data

Abstract Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.

Ultrathin Low Energy Simox for Low Cost, High Density Applications

1993 ◽  
Vol 316 ◽  
Author(s):  
Fereydoon Namavar ◽  
N.M. Kalkhoran ◽  
A. Cremins
Keyword(s):  
Low Cost ◽  
Electrical Characterization ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Great Promise ◽  
Fully Depleted ◽  
Device Structures ◽  
Radiation Hard ◽  
Standard Energy

ABSTRACTSilicon-on-insulator (SOI) materials made by standard energy (150 to 200 keV) separation by implantation of oxygen (SIMOX) processes have shown great promise for meeting the needs of radiation-hard microelectronics. Since much smaller doses are required, low energy SIMOX (LES) reduces cost, improves radiation hardness, and increases the throughput of any ion implanter. The process can also produce high quality thin SIMOX structures that are of particular interest for fully depleted and submicron device structures. In this paper, we address the formation as well as the material and electrical characterization of LES wafers and compare them with standard SIMOX wafers.

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