Fabrication of metrology test structures for future technology nodes using high-resolution variable-shaped e-beam direct write

SEM-Based Nanoprobing on 40, 32 and 28 nm CMOS Devices Challenges for Semiconductor Failure Analysis

ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2013p0217 ◽

2013 ◽

Author(s):

Erik Paul ◽

Holger Herzog ◽

Sören Jansen ◽

Christian Hobert ◽

Eckhard Langer

Keyword(s):

Electron Microscope ◽

High Resolution ◽

Scanning Electron Microscope ◽

Failure Analysis ◽

Case Studies ◽

State Of The Art ◽

Root Cause ◽

Highly Efficient ◽

Technology Nodes ◽

Scanning Electron

Abstract This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

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Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator

MRS Proceedings ◽

10.1557/proc-0912-c01-10 ◽

2006 ◽

Vol 912 ◽

Cited By ~ 1

Author(s):

Justin J Hamilton ◽

Erik JH Collart ◽

Benjamin Colombeau ◽

Massimo Bersani ◽

Damiano Giubertoni ◽

...

Keyword(s):

Structural Properties ◽

Solid Phase ◽

Silicon Film ◽

Silicon On Insulator ◽

Bulk Silicon ◽

Defect Band ◽

Future Technology ◽

Ultrashallow Junctions ◽

P Type ◽

Technology Nodes

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.

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Correction: High-Resolution Patterning of Hydrogels in Three Dimensions using Direct-Write Photofabrication for Cell Guidance

Advanced Functional Materials ◽

10.1002/adfm.201090036 ◽

2010 ◽

Vol 20 (9) ◽

pp. n/a-n/a ◽

Cited By ~ 2

Author(s):

Stephanie K. Seidlits ◽

Christine E. Schmidt ◽

Jason B. Shear

Keyword(s):

High Resolution ◽

Three Dimensions ◽

Direct Write ◽

Cell Guidance

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Reduction of CNT Interconnect Resistance for the Replacement of Cu for Future Technology Nodes

IEEE Transactions on Nanotechnology ◽

10.1109/tnano.2011.2148725 ◽

2012 ◽

Vol 11 (1) ◽

pp. 56-62 ◽

Cited By ~ 9

Author(s):

Jonathan W. Ward ◽

Jonathan Nichols ◽

Timothy B. Stachowiak ◽

Quoc Ngo ◽

E. James Egerton

Keyword(s):

Future Technology ◽

Technology Nodes ◽

Interconnect Resistance

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Aerosol Printing of High Resolution Films for LTCC-Multilayer Components

Journal of Microelectronics and Electronic Packaging ◽

10.4071/imaps.340 ◽

2012 ◽

Vol 9 (3) ◽

pp. 133-137 ◽

Cited By ~ 3

Author(s):

Martin Ihle ◽

Uwe Partsch ◽

Sindy Mosch ◽

Adrian Goldberg

Keyword(s):

High Resolution ◽

High Frequency ◽

High Reliability ◽

Direct Write ◽

Printing Technology ◽

Fine Line ◽

Aerosol Printing ◽

Fine Structures ◽

Cost Efficient ◽

Printing Parameters

For the electronic packaging of sensor stable and cost-efficient fine line printing technologies on LTCC and high frequency laminates are needed. Especially common technologies like screen printing and thin film techniques are unsuitable for fine structures or too expensive. In addition, there is no direct write technology for 3D LTCC designs as well as for high reliability cofiring structures. Closing this gap, aerosol printing technology is used to print high resolution conductors on planar and nonplanar substrates. Aerosol printing is a direct write noncontact printing technology of functional layers. After pneumatic atomization, the ink is transformed into 1–5 μm droplets. The resulting continuous aerosol stream is focused by a sheath gas in the printing head. Thus, the long standoff distance between the substrate and the deposition tip of max. 5 mm allows 3D printing on nonplanar substrates. With optimized inks and printing parameters, line widths of 10 μm are achievable. This paper will present applications for aerosol printed functional layers on LTCC. These are, for example, aerosol printed films embedded in cofired LTCC, fine line structures for high frequency applications, and the evaluation of printed 3D structures like LTCC stairways. Furthermore, the 90° contact of unconventional sensor designs will be presented.

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