Modelling MOSFET gate length variability for future technology nodes

2008 ◽  
Vol 205 (11) ◽  
pp. 2541-2543
Author(s):  
G. P. Patsis
Keyword(s):  
Gate Length ◽  
Future Technology ◽  
Technology Nodes

Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator

2006 ◽  
Vol 912 ◽  
Author(s):  
Justin J Hamilton ◽  
Erik JH Collart ◽  
Benjamin Colombeau ◽  
Massimo Bersani ◽  
Damiano Giubertoni ◽  
...  
Keyword(s):  
Structural Properties ◽  
Solid Phase ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
Defect Band ◽  
Future Technology ◽  
Ultrashallow Junctions ◽  
P Type ◽  
Technology Nodes

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.

Reduction of CNT Interconnect Resistance for the Replacement of Cu for Future Technology Nodes

2012 ◽  
Vol 11 (1) ◽  
pp. 56-62 ◽  
Author(s):  
Jonathan W. Ward ◽  
Jonathan Nichols ◽  
Timothy B. Stachowiak ◽  
Quoc Ngo ◽  
E. James Egerton
Keyword(s):  
Future Technology ◽  
Technology Nodes ◽  
Interconnect Resistance

Photomask etch challenges for future technology nodes

2006 ◽  
Author(s):  
Madhavi Chandrachood ◽  
Michael Grimbergen ◽  
Toi Yue B. Leung ◽  
Keven Yu ◽  
Renee Koch ◽  
...  
Keyword(s):  
Future Technology ◽  
Technology Nodes

scholarly journals Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 53196-53202 ◽  
Author(s):  
Daniel Nagy ◽  
Gabriel Espineira ◽  
Guillermo Indalecio ◽  
Antonio J. Garcia-Loureiro ◽  
Karol Kalna ◽  
...  
Keyword(s):  
Future Technology ◽  
Technology Nodes

Performance analysis of nanowire and nanosheet NCFETs for future technology nodes

2021 ◽  
Author(s):  
Fahimul Islam Sakib ◽  
Md. Azizul Hasan ◽  
Mainul Hossain
Keyword(s):  
Performance Optimization ◽  
Computer Aided Design ◽  
Single Channel ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Differential Resistance ◽  
Future Technology ◽  
Aided Design ◽  
Technology Nodes ◽  
Tcad Simulations

Abstract Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In addition to single channel NC-NSFETs and NC-NWFETs, those, with vertically stacked NSs and NWs, have been examined for the same layout footprint (LF). Results show that NC-NSFETs can achieve lower subthreshold swing (SS) and higher ON-current (ION ) than NC-NWFET of comparable device dimensions. However, NC-NWFETs show slightly higher ION/IOFF ratio. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths as small as 10 nm. The results presented here can, therefore, provide useful insights for performance optimization of NC-NWFETs and NC-NSFETs, in ultra-scaled and high-density logic applications, for 7 nm and beyond technology nodes.

Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP, and WS2-Based n-MOSFETs for Future Technology Nodes—Part I: Device-Level Comparison

2019 ◽  
Vol 66 (8) ◽  
pp. 3608-3613
Author(s):  
Tarun Kumar Agarwal ◽  
Martin Rau ◽  
Iuliana Radu ◽  
Mathieu Luisier ◽  
Wim Dehaene ◽  
...  
Keyword(s):  
Performance Comparison ◽  
Future Technology ◽  
Technology Nodes

The evolution of standard cell libraries for future technology nodes

2011 ◽  
Vol 12 (3) ◽  
pp. 235-256 ◽  
Author(s):  
James Alfred Walker ◽  
James A. Hilder ◽  
Dave Reid ◽  
Asen Asenov ◽  
Scott Roy ◽  
...  
Keyword(s):  
Standard Cell ◽  
Future Technology ◽  
Technology Nodes

Optimization of MSB for future technology nodes

2012 ◽  
Author(s):  
Hans-Joachim Doering ◽  
Thomas Elster ◽  
Matthias Klein ◽  
Joachim Heinitz ◽  
Marc Schneider ◽  
...  
Keyword(s):  
Future Technology ◽  
Technology Nodes

A CMOS Compatible Carbon Nanotube Growth Approach

2011 ◽  
Vol 1284 ◽  
Author(s):  
Daire Cott ◽  
Masahito Sugiura ◽  
Nicolo Chiodarelli ◽  
Kai Arstila ◽  
Philipe M. Vereecken ◽  
...  
Keyword(s):  
Carbon Nanotubes ◽  
Carbon Nanotube ◽  
Metallic Nanoparticles ◽  
Elevated Temperatures ◽  
Microwave Plasma ◽  
High Density ◽  
Growth Environment ◽  
Future Technology ◽  
Cmos Compatible ◽  
Technology Nodes

ABSTRACTIn future technology nodes, 22nm and below, carbon nanotubes (CNTs) may provide a viable alternative to Cu as an interconnect material. CNTs exhibit a current carrying capacity (up to 109 A/cm2), whilst also providing a significantly higher thermal conductivity (SWCNT ~ 5000 WmK) over Copper (106 A/cm2 and ~400WmK). However, exploiting such properties of CNTs in small vias is a challenging endeavor. In reality, to outperform Cu in terms of a reduction in via resistance alone, densities in the order of 1013 CNTs/cm2 are required. At present, conventional thermal CVD of carbon nanotubes is carried out at temperatures far in excess of CMOS temperature limits (400 C). Furthermore, high density CNT bundles are most commonly grown on insulating supports such as Al2O3 and SiO2 as they can effectively stabilize metallic nanoparticles at elevated temperatures but this limits their application in electronic devices. To circumvent these obstacles we employ a remote microwave plasma to grow high density CNTs at a temperature of 400 C on conductive underlayers such as TiN. We identify some critical factors important for high-quality CNTs at low temperatures such as control over the catalyst to underlayer interaction and plasma growth environment while presenting a fully CMOS compatible carbon nanotube synthesis approach

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