Si single electron transistor fabricated by chemical mechanical polishing

Author(s):  
Yen-Chun Lee ◽  
Vishwanath Joshi ◽  
Alexei O. Orlov ◽  
Gregory L. Snider
2006 ◽  
Vol 961 ◽  
Author(s):  
Christian Dubuc ◽  
Jacques Beauvais ◽  
Dominique Drouin

ABSTRACTWe report a single-electron transistor concept and its related process enabling the fabrication of ultrasmall junction capacitance. The method utilizes a nanodamascene approach where trenches in silicon oxide are covered with a filling material and planarized with chemical mechanical polishing. Single-electron transistors fabricated with this approach were characterized up to 433 K and demonstrated that the nanodamascene process has high resolution, is relatively simple and is highly scalable.


2001 ◽  
Vol 89 (1) ◽  
pp. 410-419 ◽  
Author(s):  
Nicole Y. Morgan ◽  
David Abusch-Magder ◽  
Marc A. Kastner ◽  
Yasuo Takahashi ◽  
Hiroyuki Tamura ◽  
...  

2021 ◽  
Vol 11 (10) ◽  
pp. 4358
Author(s):  
Hanchul Cho ◽  
Taekyung Lee ◽  
Doyeon Kim ◽  
Hyoungjae Kim

The uniformity of the wafer in a chemical mechanical polishing (CMP) process is vital to the ultra-fine and high integration of semiconductor structures. In particular, the uniformity of the polishing pad corresponding to the tool directly affects the polishing uniformity and wafer shape. In this study, the profile shape of a CMP pad was predicted through a kinematic simulation based on the trajectory density of the diamond abrasives of the diamond conditioner disc. The kinematic prediction was found to be in good agreement with the experimentally measured pad profile shape. Based on this, the shape error of the pad could be maintained within 10 μm even after performing the pad conditioning process for more than 2 h, through the overhang of the conditioner.


Author(s):  
Peili Gao ◽  
Tingting Liu ◽  
Zhenyu Zhang ◽  
Fanning Meng ◽  
Run-Ping Ye ◽  
...  

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