Enhanced Thermoelectric Cooler for On-Chip Hot Spot Cooling

2007 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen ◽  
Bao Yang
Keyword(s):  
Hot Spot ◽  
Heat Fluxes ◽  
Operating Conditions ◽  
Optimum Operating ◽  
Cooling Power ◽  
Thermoelectric Cooler ◽  
Thermoelectric Coolers ◽  
Cooling Performance ◽  
Spot Cooling ◽  
On Chip

Due to shrinking feature size and increasing transistor density, combined with the performance demanded from next-generation microprocessors, on-chip hot spots, with their associated high heat fluxes and sharp temperature gradients, have emerged as the primary driver for thermal management of today’s IC technology. This paper describes the novel use of thermoelectric coolers for on-chip hot spot cooling through the use of a copper mini-contact pad, which connects the thermoelectric cooler and the silicon chip thus concentrating the thermoelectric cooling power. A package-level numerical simulation is developed to predict the local on-chip hot spot cooling performance which can be achieved with such mini-contacts. Attention is focused on the hot spot temperature reduction associated with variations in mini-contact size and the thermoelectric element thickness, as well as the parasitic effect of the thermal contact resistance introduced by the mini-contact enhanced TEC. This numerical model and simulation results are validated by comparison to spot cooling experiments with a uniformly heated chip serving as the test vehicle. The experimental results demonstrate that a copper mini-contact pad can improve spot cooling performance by 80 ∼ 115% on a 500μm thick silicon chip under optimum operating conditions and that larger power dissipation on the chip leads to better spot cooling performance.

Mini-Contact Enhanced Thermoelectric Coolers for On-Chip Hot Spot Cooling

2009 ◽  
Vol 30 (9) ◽  
pp. 736-743 ◽  
Author(s):  
Peng Wang ◽  
Bao Yang ◽  
Avram Bar-Cohen
Keyword(s):  
Hot Spot ◽  
Thermoelectric Coolers ◽  
Spot Cooling ◽  
On Chip

Effect of Thermal Contact Resistance on Optimum Mini-Contact TEC Cooling of On-Chip Hot Spots

2009 ◽  
Author(s):  
Viatcheslav Litvinovitch ◽  
Avram Bar-Cohen
Keyword(s):  
Contact Resistance ◽  
Thermal Management ◽  
Hot Spots ◽  
High Performance ◽  
Thermal Contact Resistance ◽  
Hot Spot ◽  
Thermal Contact ◽  
Heat Fluxes ◽  
Thermoelectric Coolers ◽  
On Chip

Shrinking feature size and increasing transistor density, combined with the high performance demanded from next-generation microprocessors and other electronic components, have lead to the emergence of severe on-chip “hot spots,” with heat fluxes approaching — and at times exceeding — 1 kW/cm2. The cost-effective thermal management of such chips requires the introduction and refinement of novel cooling techniques. Mini-contact enhanced, miniaturized thermoelectric coolers (TECs) have been shown to be a viable approach for the remediation of on-chip hot spots, but their performance is constrained by the thermal resistance introduced by the attachment of this thermal management device. This paper uses a detailed finite-element package-level model to examine the parasitic effects of the thermal contact resistance (at the interfaces of the mini-contact and TEC) on the cooling efficacy of this thermal solution. Particular attention is devoted to the deleterious effect of contact resistance on the thermoelectric leg height and the mini-contact size required to achieve the greatest hot spot temperature reduction on the chip. Data from experiments with TECs (with a leg height of 130 μm) combined with several sizes of mini-contact pads, are used to validate the modeling approach and the overall conclusions.

Investigation of On-Chip Hot Spot Cooling Using Microchannel Heat Sink

2013 ◽  
Vol 455 ◽  
pp. 466-469
Author(s):  
Yun Chuan Wu ◽  
Shang Long Xu ◽  
Chao Wang
Keyword(s):  
Heat Flux ◽  
Heat Sink ◽  
Hot Spots ◽  
Hot Spot ◽  
High Heat ◽  
High Heat Flux ◽  
Microchannel Heat Sink ◽  
Three Dimensional Model ◽  
Spot Cooling ◽  
On Chip

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.

JOULE HEATING EFFECT REDUCTION OF AN ELECTROMAGNET SYSTEM UTILIZING ON-CHIP MAGNETIC CORE

2016 ◽  
Vol 78 (8-4) ◽  
Author(s):  
Ummikalsom Abidin ◽  
Jumril Yunas ◽  
Burhanuddin Yeop Majlis
Keyword(s):  
Joule Heating ◽  
Temperature Rise ◽  
Magnetic Core ◽  
Operating Conditions ◽  
Optimum Operating ◽  
Pdms Layer ◽  
Heating Effect ◽  
Joule Heating Effect ◽  
Magnet Wire ◽  
On Chip

Joule heating effect is substantial in an electromagnet system due to high density current from current-carrying conductor for high magnetic field generation. In Lab-on-chip (LoC) Magnetically Activated Cell Sorting (MACS) device, Joule heating effect generating high temperature and affecting the biological cells viability is investigated. The temperature rise of the integrated system was measured using resistance temperature detector, RTD Pt100. Three temperature rise conditions which are from the bare spiral-shaped magnet wire, the combination of magnet wire and on-chip magnetic core and combination of magnet wire, on-chip magnetic core and 150 mm polydimethylsiloxane (PDMS) layer have been investigated.  The combination of electromagnet of spiral-shaped magnet wire coil and on-chip magnetic core has reduced the temperature significantly which are, ~ 38 %  and ~ 26 % with magnet wire winding, N = 10 (IDC = 3.0 A, t = 210 s) and N = 20 (IDC = 2.5 A, t = 210 s) respectively. The reduced Joule heating effect is expected due to silicon chip of high thermal conductivity material enable fast heat dissipation to the surrounding.  Therefore, the integration of electromagnet system and on-chip magnetic core has the potential to be used as part of LoC MACS system provided the optimum operating conditions are determined

Inverse Design of Cooling of Electronic Chips Subject to Specified Hot Spot Temperature and Coolant Inlet Temperature

2015 ◽  
Author(s):  
Sohail R. Reddy ◽  
George S. Dulikravich
Keyword(s):  
Heat Flux ◽  
Hot Spot ◽  
Heat Fluxes ◽  
Operating Conditions ◽  
Heat Transfer Analysis ◽  
Maximum Temperature ◽  
Fluid Temperature ◽  
Cooling Fluid ◽  
Pin Fin ◽  
The Given

Most methods for designing electronics cooling schemes do not offer the information on what levels of heat fluxes are maximally possible to achieve with the given material, boundary and operating conditions. Here, we offer an answer to this inverse problem posed by the question below. Given a micro pin-fin array cooling with these constraints: - given maximum allowable temperature of the material, - given inlet cooling fluid temperature, - given total pressure loss (pumping power affordable), and - given overall thickness of the entire electronic component, find out the maximum possible average heat flux on the hot surface and find the maximum possible heat flux at the hot spot under the condition that the entire amount of the inputted heat is completely removed by the cooling fluid. This problem was solved using multi-objective constrained optimization and metamodeling for an array of micro pin-fins with circular, airfoil and symmetric convex cross sections that is removing all the heat inputted via uniform background heat flux and by a hot spot. The goal of this effort was to identify a cooling pin-fin shape and scheme that is able to push the maximum allowable heat flux as high as possible without the maximum temperature exceeding the specified limit for the given material. Conjugate heat transfer analysis was performed on each of the randomly created candidate configurations. Response surfaces based on Radial Basis Functions were coupled with a genetic algorithm to arrive at a Pareto frontier of best trade-off solutions. The Pareto optimized configuration indicates the maximum physically possible heat fluxes for specified material and constraints.

Active Hot Spot Cooling Controlled by Single-Sided Electrowetting-on-Dielectric (SEWOD)

2012 ◽  
Author(s):  
Sung-Yong Park ◽  
Jiangtao Cheng ◽  
Chung-Lung (C.-L. ) Chen
Keyword(s):  
Heat Transfer ◽  
Fluid Transport ◽  
Hot Spot ◽  
Two Phase ◽  
Electrowetting On Dielectric ◽  
Transfer Capability ◽  
Heat Transfer Capability ◽  
Spot Cooling ◽  
On Chip ◽  
Two Phase Cooling

Electrowetting-on-dielectric (EWOD) has attracted as one of the effective on-chip cooling technologies. It enables rapid transport of coolant droplets and heat transfer from target heat sources, while consuming extremely low power for fluid transport. However, a sandwiched configuration in conventional EWOD devices only allows sensible heat transfer, which very limits heat transfer capability of the device. In this paper, we report a novel single-sided EWOD (SEWOD) technology that enables two-phase cooling on a single-sided plate. As a result, heat transfer capability of the SEWOD device can be significantly enhanced. A complete set of droplet manipulation functions necessary for active hot spot cooling has been achieved on SEWOD. Hot spot surface modification to hydrophilic makes a droplet stick on a hot spot and maximize its contact area, greatly improving thermal rejection capability of the device. We have demonstrated two-phase cooling on SEWOD. With successive transportation of four droplets with a volume of 30 μL, the hot spot temperature that was initially heated up to 172°C was able to be stably maintained below 100 °C for 475s. This novel SEWOD-driven cooling technique promises to potentially function as a wickless vapor chamber with enhanced thermal managing capabilities.

Thermoelectric Coolers for Hotspot Thermal Management of 3D Stacked Chips

2011 ◽  
Author(s):  
Matthew Redmond ◽  
Kavin Manickaraj ◽  
Owen Sullivan ◽  
Satish Kumar
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Power Density ◽  
Hot Spot ◽  
Thermal Contact ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermoelectric Coolers ◽  
Vertical Coupling ◽  
Spot Cooling

Three dimensional (3D) technologies with stacked chips have the potential to provide new chip architecture, improved device density, performance, efficiency, and bandwidth. Their increased power density also can become a daunting challenge for heat removal. Furthermore, power density can be highly non-uniform leading to time and space varying hotspots which can severely affect performance and reliability of the integrated circuits. Thus, it is important to mitigate thermal gradients on chip while considering the associated cooling costs. One method of thermal management currently under investigation is the use of superlattice thermoelectric coolers (TECs) which can be employed for on demand and localized cooling. In this paper, a detailed 3D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is studied in order to investigate the efficacy of TECs in hot spot cooling for a 3D technology. We observe up to 14.6 °C of cooling at a hot spot inside the package by TECs. A strong vertical coupling has been observed between the TECs located in top and bottom dies. Bottom TECs can detrimentally heat the top hotspots in both steady state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between the TEC and heat spreader are shown to have a crucial effect on TEC performance inside the package. We observed that square root current pulse can provide very efficient short-duration transient cooling at hotspots.

Sign in / Sign up

Export Citation Format

Share Document