Effect of Thermal Contact Resistance on Optimum Mini-Contact TEC Cooling of On-Chip Hot Spots

2009 ◽  
Author(s):  
Viatcheslav Litvinovitch ◽  
Avram Bar-Cohen
Keyword(s):  
Contact Resistance ◽  
Thermal Management ◽  
Hot Spots ◽  
High Performance ◽  
Thermal Contact Resistance ◽  
Hot Spot ◽  
Thermal Contact ◽  
Heat Fluxes ◽  
Thermoelectric Coolers ◽  
On Chip

Shrinking feature size and increasing transistor density, combined with the high performance demanded from next-generation microprocessors and other electronic components, have lead to the emergence of severe on-chip “hot spots,” with heat fluxes approaching — and at times exceeding — 1 kW/cm2. The cost-effective thermal management of such chips requires the introduction and refinement of novel cooling techniques. Mini-contact enhanced, miniaturized thermoelectric coolers (TECs) have been shown to be a viable approach for the remediation of on-chip hot spots, but their performance is constrained by the thermal resistance introduced by the attachment of this thermal management device. This paper uses a detailed finite-element package-level model to examine the parasitic effects of the thermal contact resistance (at the interfaces of the mini-contact and TEC) on the cooling efficacy of this thermal solution. Particular attention is devoted to the deleterious effect of contact resistance on the thermoelectric leg height and the mini-contact size required to achieve the greatest hot spot temperature reduction on the chip. Data from experiments with TECs (with a leg height of 130 μm) combined with several sizes of mini-contact pads, are used to validate the modeling approach and the overall conclusions.

Thermoelectric Self-Cooling on Germanium Chip

2010 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen
Keyword(s):  
Thermal Management ◽  
Hot Spots ◽  
Hot Spot ◽  
Thermal Contact ◽  
Chip Thickness ◽  
Management Approach ◽  
High Flux ◽  
Thermo Electric ◽  
Wide Range ◽  
On Chip

Growing interest in germanium solid-state devices is raising concern over the effects of on-chip, micro-scaled, high flux hot spot on the reliability and performance of germanium chips. Current thermal management technology offers few choices for such on-chip hot spot remediation. However, the good thermo-electric properties of single crystal germanium support the development of a novel thermal management approach, relying on thermoelectric self-cooling by an electric current flowing in a thin planar layer on the back of the germanium chip. Use of metal-on-germanium fabrication techniques can yield a very low thermal contact resistance at the micro cooler/chip interface and the current flow can transfer the energy absorbed from a hot spot to the edge of the chip, thus substantially reducing the detrimental effect of thermoelectric heating on the temperature of the active circuitry. In this paper three-dimensional thermo-electric simulations are used to investigate the self-cooling of hot spots on a germanium chip for a wide range of input current, doping concentration, hot spot heat flux, micro cooler size, and germanium chip thickness. Results suggest that localized thermoelectric self-cooling on the germanium chip can significantly reduce the temperature rise resulting from micro-scaled high-flux hot spots.

Simplified Thermal Model of Silicon Thermoelectric Microcooler for On-Chip Hot Spot Remediation

2007 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen
Keyword(s):  
Thermal Management ◽  
Material Properties ◽  
Hot Spots ◽  
Hot Spot ◽  
Design Tool ◽  
The Novel ◽  
Thermo Electric ◽  
Design And Optimization ◽  
Conventional Cooling ◽  
On Chip

Thermal management of on-chip hot spots has become an increasing challenge in recent years because such localized high flux hot spots can not be effectively removed by conventional cooling techniques. The authors have recently explored the novel use of the silicon chip itself as a solid state thermoelectric micrcooler (μTEC) for hot spot thermal management. This paper describes the development and application of a thermo-electric design tool based on closed-form equations for the primary variables. This tool can be used to effectively reduce the complexity and required time for the design and optimization of the silicon microcooler geometry and material properties for on-chip hot spot remediation.

Measuring the Thermal Contact Resistance Between Cu Foams and Substrates for On-Chip Cooling Applications in Data Centers

2021 ◽  
Author(s):  
Lucas Arrivo ◽  
Steven Schon ◽  
Aaron P. Wemhoff
Keyword(s):  
Heat Transfer ◽  
Contact Resistance ◽  
Data Centers ◽  
Thermal Contact Resistance ◽  
Thermal Contact ◽  
Metal Foams ◽  
Heat Transfer Area ◽  
Chip Cooling ◽  
Cold Plates ◽  
On Chip

Abstract Data centers housing high performance computing equipment have large and growing rack densities, which pushes the limits of traditional air cooling technologies because of limited heat transfer coefficients. Therefore, on-chip cooling using so-called cold plates is emerging as a necessary cooling option for high-density electronics. The use of mini-channels or pins fins to enhance internal heat transfer area inside cold plates requires extensive micro-machining that is relatively time consuming and expensive for mass production. As an alternative approach, inserting and bonding pre-manufactured metal foams into hollow bodies are explored as a potentially inexpensive means to enhance the interior heat transfer area of cold plates. One key aspect of the performance of metal foams in cold plates is the thermal contact resistance in the bonding between the foam and the substrate. This project predicts the contact resistance using measurements of different foam types (pure Cu and Cu with oxide), porosities (63%, 80%, 93%, and 95%) and thicknesses (4 mm, 8 mm, and 10 mm). These measurements are carried out with and without the use of thermal interface material (TIM) pads. A theory is proposed and implemented to estimate the contact and foam thermal resistances, but further work is needed to gain confidence in the results. Observations suggest that different thermal behavior is seen for the Cu foams compared to the Cu with oxide foams, and that the use of TIM pads can achieve 10x to 40x reduction in overall thermal resistance for highly porous foams bonded on Cu substrates.

Thermoelectric Coolers for Hotspot Thermal Management of 3D Stacked Chips

2011 ◽  
Author(s):  
Matthew Redmond ◽  
Kavin Manickaraj ◽  
Owen Sullivan ◽  
Satish Kumar
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Power Density ◽  
Hot Spot ◽  
Thermal Contact ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermoelectric Coolers ◽  
Vertical Coupling ◽  
Spot Cooling

Three dimensional (3D) technologies with stacked chips have the potential to provide new chip architecture, improved device density, performance, efficiency, and bandwidth. Their increased power density also can become a daunting challenge for heat removal. Furthermore, power density can be highly non-uniform leading to time and space varying hotspots which can severely affect performance and reliability of the integrated circuits. Thus, it is important to mitigate thermal gradients on chip while considering the associated cooling costs. One method of thermal management currently under investigation is the use of superlattice thermoelectric coolers (TECs) which can be employed for on demand and localized cooling. In this paper, a detailed 3D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is studied in order to investigate the efficacy of TECs in hot spot cooling for a 3D technology. We observe up to 14.6 °C of cooling at a hot spot inside the package by TECs. A strong vertical coupling has been observed between the TECs located in top and bottom dies. Bottom TECs can detrimentally heat the top hotspots in both steady state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between the TEC and heat spreader are shown to have a crucial effect on TEC performance inside the package. We observed that square root current pulse can provide very efficient short-duration transient cooling at hotspots.

Array of Thermoelectric Coolers for On-Chip Thermal Management

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Owen Sullivan ◽  
Man Prakash Gupta ◽  
Saibal Mukhopadhyay ◽  
Satish Kumar
Keyword(s):  
Steady State ◽  
Current Pulse ◽  
Hot Spots ◽  
Hot Spot ◽  
High Amplitude ◽  
Peak Temperature ◽  
Thermoelectric Coolers ◽  
Electronic Package ◽  
Current Pulses ◽  
On Chip

Site-specific on-demand cooling of hot spots in microprocessors can reduce peak temperature and achieve a more uniform thermal profile on chip, thereby improve chip performance and increase the processor’s life time. An array of thermoelectric coolers (TECs) integrated inside an electronic package has the potential to provide such efficient cooling of hot spots on chip. This paper analyzes the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way. Our computational analysis of an electronic package with multiple TECs shows a strong conductive coupling among active TECs during steady-state operation. Transient operation of TECs is capable of driving cold-side temperatures below steady-state values. Our analysis on TEC arrays using current pulses shows that the effect of TEC coupling on transient cooling is weak. Various pulse profiles have been studied to illustrate the effect of shape of current pulse on the operation of TECs considering crucial parameters such as total energy consumed in TECs peak temperature on the chip, temperature overshoot at the hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be the most effective with maximum cooling and at half the energy expenditure in comparison to a constant current pulse. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the transient cooling using high amplitude current pulses is beneficial for short term infrequent hot spots, but high amplitude current pulse cannot be used for very frequent or long lasting hot spots.

Enhanced Thermoelectric Cooler for On-Chip Hot Spot Cooling

2007 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen ◽  
Bao Yang
Keyword(s):  
Hot Spot ◽  
Heat Fluxes ◽  
Operating Conditions ◽  
Optimum Operating ◽  
Cooling Power ◽  
Thermoelectric Cooler ◽  
Thermoelectric Coolers ◽  
Cooling Performance ◽  
Spot Cooling ◽  
On Chip

Due to shrinking feature size and increasing transistor density, combined with the performance demanded from next-generation microprocessors, on-chip hot spots, with their associated high heat fluxes and sharp temperature gradients, have emerged as the primary driver for thermal management of today’s IC technology. This paper describes the novel use of thermoelectric coolers for on-chip hot spot cooling through the use of a copper mini-contact pad, which connects the thermoelectric cooler and the silicon chip thus concentrating the thermoelectric cooling power. A package-level numerical simulation is developed to predict the local on-chip hot spot cooling performance which can be achieved with such mini-contacts. Attention is focused on the hot spot temperature reduction associated with variations in mini-contact size and the thermoelectric element thickness, as well as the parasitic effect of the thermal contact resistance introduced by the mini-contact enhanced TEC. This numerical model and simulation results are validated by comparison to spot cooling experiments with a uniformly heated chip serving as the test vehicle. The experimental results demonstrate that a copper mini-contact pad can improve spot cooling performance by 80 ∼ 115% on a 500μm thick silicon chip under optimum operating conditions and that larger power dissipation on the chip leads to better spot cooling performance.

Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies

2013 ◽  
Vol 135 (2) ◽  
Author(s):  
Wataru Nakayama
Keyword(s):  
Hot Spots ◽  
High Performance ◽  
Thermal Environment ◽  
Hot Spot ◽  
Air Cooling ◽  
Multicore Processor ◽  
Temperature Contrast ◽  
On Chip ◽  
Heat Spreading ◽  
Level Analysis

The objective of this study is to understand the effects of various parameters involved in the chip design and cooling on the occurrence of hot spots on a multicore processor chip. The thermal environment for the die is determined by the cooling design which differs distinctly between different classes of electronic equipment. In the present study, like many other hot spot studies, the effective heat transfer coefficient represents the thermal environment for the die, but, its representative values are derived for different cooling schemes in order to examine in what classes of electronic equipment the hot spot concern grows. The cooling modes under study are high-performance air-cooling, high-performance liquid-cooling, conventional air-cooling, and oil-cooling in infrared radiation (IR) thermography setup. Temperature calculations were performed on a model which is designed to facilitate the study of several questions that have not been fully addressed in the existing literature. These questions are concerned with the granularity of power and temperature distributions, thermal interactions between circuits on the die, the roles of on-chip wiring layer and the buried dioxide in heat spreading, and the mechanism of producing temperature contrast across the die. The main results of calculations are the temperature of the target spot and the temperature contrast across the die. Temperature contrasts are predicted in a range 10–25 K, and the results indicate that a major part of the temperature contrast is formed at a granularity corresponding to the size of functional units on actual microprocessor chips. At a fine granularity level and under a scenario of high power concentration, the on-chip wiring layer and the buried oxide play some roles in heat spreading, but their impact on the temperature is generally small. However, the details of circuits need to be taken into account in future studies in order to investigate the possibility of nanometer-scale hot spots. Attention is also called to the need to understand the effect of temperature nonuniformity on the processor performance for which low temperature at inactive cells makes a major contribution. In contrast to the situation for the die under forced convection cooling, the die in passively cooled compact equipment is in distinctly different thermal environment. Strong thermal coupling between the die and the system structure necessitates the integration of package and system level analysis with the die-level analysis.

Thermoelectric Coolers for Thermal Gradient Management on Chip

2010 ◽  
Author(s):  
Owen Sullivan ◽  
Man Prakash Gupta ◽  
Saibal Mukhopadhyay ◽  
Satish Kumar
Keyword(s):  
Current Pulse ◽  
Hot Spots ◽  
Hot Spot ◽  
Thermal Contact ◽  
Life Time ◽  
Peak Temperature ◽  
Constant Current ◽  
Pulse Profile ◽  
Thermal Profile ◽  
Thermoelectric Coolers

Site-specific and on-demand cooling of hot spots in the microprocessors can provide efficient cooling solution, improve its performance and increase its life time by reducing peak temperature and achieving more uniform thermal profile on the chip. Thermoelectric coolers (TEC) have the potential to provide such efficient cooling of hot spots on a chip. We investigate pulse cooling behavior of ultra-thin multiple TEC devices integrated inside the electronic package on the active side of a chip below the heat spreader. Various pulse profiles have been studied to obtain optimal shape of the current pulse in order to efficiently operate TECs considering crucial parameters such as the total energy consumed in TECs, peak temperature on the chip, temperature overshoot at hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be most effective with maximum cooling and half the energy expenditure in comparison to a constant current pulse. It has been observed that high thermal contact resistances can entirely negate the transient cooling effect of the TECs. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the temperature of the hot spots can be retained below a threshold using transient current pulses through the TECs. This underlines the benefits of using multiple TECs for hot spot cooling in order to obtain favorable thermal profile on the chip in an energy efficient way.

Sign in / Sign up

Export Citation Format

Share Document