Measurement of Stress and Delamination in Flip Chip on Laminate Assemblies

2003 ◽  
Author(s):  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
D. Scott Copeland ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Flip Chip ◽  
Acoustic Microscopy ◽  
Valuable Insight ◽  
Stress Distributions ◽  
Environmental Testing ◽  
Stress Measurements ◽  
Piezoresistive Sensors ◽  
Die Stress ◽  
Test Chips ◽  
Stress Variations

Mechanical stress distributions in packaged silicon die that have resulted during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, an overview of recent measurements made in flip chip on laminate assemblies with (111) silicon test chips is presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. The experimental stress measurements in the flip chip samples were then correlated with finite element predictions for the tested configurations. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from −40 to +150°C. Finally the stress variations occurring during thermal cycling from −40 to +125°C have been characterized. These measurements have been correlated with the delaminations occurring at the die passivation to underfill interface measured using C-mode Scanning Acoustic Microscopy (C-SAM). Using the measurements and numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

Piezoresistive Stress Sensors for Structural Analysis of Electronic Packages

1991 ◽  
Vol 113 (3) ◽  
pp. 203-215 ◽  
Author(s):  
D. A. Bittle ◽  
J. C. Suhling ◽  
R. E. Beaty ◽  
R. C. Jaeger ◽  
R. W. Johnson
Keyword(s):  
Integrated Circuit ◽  
Structural Reliability ◽  
Lattice Structure ◽  
Three Dimensional ◽  
Electronic Packages ◽  
Cubic Symmetry ◽  
Piezoresistive Sensors ◽  
Stress Sensors ◽  
Die Stress ◽  
Test Chips

Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the theory of conduction in piezoresistive materials is reviewed and the basic equations applicable to the design of stress sensors on test chips are presented. General expressions are obtained for the stress-induced resistance changes which occur in arbitrarily oriented one-dimensional filamentary conductors fabricated out of crystals with cubic symmetry and diamond lattice structure. These relations are then applied to obtain basic results for stressed in-plane resistors fabricated into the surface of (100) and (111) oriented silicon wafers. Sensor rosettes developed by previous researchers for each of these wafer orientations are reviewed and more powerful rosettes are presented along with the equations needed for their successful application. In particular, a new sensor rosette fabricated on (111) silicon is presented which can measure the complete three-dimensional stress state at points on the surface of a die

Measurement of die stress distributions in flip chip CBGA packaging

2010 ◽  
Author(s):  
Jordan Roberts ◽  
Safina Hussain ◽  
M. Kaysar Rahim ◽  
Mohammad Motalab ◽  
Jeffrey C. Suhling ◽  
...  
Keyword(s):  
Flip Chip ◽  
Stress Distributions ◽  
Die Stress

In Situ Chip Stress Extractions for LFBGA Packages Through Piezoresistive Sensors

2009 ◽  
Vol 131 (3) ◽  
Author(s):  
Ben-Je Lwo ◽  
Jeng-Shian Su ◽  
Hsien Chung
Keyword(s):  
Stress Measurements ◽  
Piezoresistive Sensors ◽  
Stress Sensors ◽  
Compressive Stresses ◽  
Fine Pitch ◽  
Low Profile ◽  
Quad Flat Package ◽  
On Chip ◽  
Test Chips

Piezoresistive sensors have been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, test chips with piezoresistive stress sensors, diode temperature sensors as well as heaters were first designed, fabricated, and calibrated. We next packaged the test chips into low profile, fine pitch ball grid array (LFBGA) packaging with 196 balls and measured the stresses on chip surfaces inside the packaging. After measuring the packaging induced stress as well as the stress under stable environmental temperature rises, it was found that compressive stresses were obtained at room temperature, and the stresses were relaxed as temperature went up at a rate between 0.45 MPa/°C and 0.60 MPa/°C. For thermo-stress experiments, the temperatures on chip surfaces at different power levels were measured, and compressive chip stresses were first extracted. As the chip power increased, the compressive stresses became tensions. Since the LFBGA structure is thinner with higher packaging efficiency, different results from our earlier plastic quad flat package stress measurements were observed and discussed. In addition, the final comparisons between the experimental data and the finite element simulations show good consistency.

Characterization of Die Stresses in CBGA Packages due to Component Assembly and Heat Sink Clamping

2011 ◽  
Author(s):  
Jordan C. Roberts ◽  
Mohammad Motalab ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Heat Sink ◽  
Flip Chip ◽  
Solder Joints ◽  
Ceramic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Interconnects ◽  
Die Stress ◽  
Free Solder ◽  
Test Chips

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, we have used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of the CBGA assembly process, as well as due to heat sink clamping. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses have been found to increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). Levels exceeding 500 MPa have been observed for extremely high heat sink clamping forces. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. A metallic lid and second level solder balls were attached to complete the flip chip ceramic BGA components. After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. Finally, CBGAs with the stress sensing chips were soldered to organic PCB test boards. A simulated heat sink loading was then applied, and the stresses were measured as a function of the clamping force. The heat sink clamping pressure distribution was monitored using in-situ resistive sensors in the TIM2 position between the lid and heat sink. The measured stress changes due to heat sink clamping where correlated with finite element simulations. With suitable detail in the models, excellent correlation has been obtained.

Characterization of Die Stress Distributions in Area Array Flip Chip Packaging

2009 ◽  
Author(s):  
Jordan Roberts ◽  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Power ◽  
Temperature Cycling ◽  
Aging Effects ◽  
Area Array ◽  
Power Cycling ◽  
Die Stress ◽  
On Chip ◽  
Test Chips

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during thermal cycling and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach also allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, initial experiments have been performed to analyze the effects of thermal cycling and power cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). Power cycling of selected parts was performed by exciting the on-chip heaters on the test chips with power levels typical of microprocessor die. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show some cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of temperature cycling duration are currently being correlated with the delaminations occurring at the interfaces between the die and underfill and the die and lid adhesive. In addition, finite element models of the packages are being developed and correlated with the data.

Characterization of Compressive Die Stresses in CBGA Microprocessor Packaging Due to Component Assembly and Heat Sink Clamping

2012 ◽  
Vol 134 (3) ◽  
Author(s):  
Jordan C. Roberts ◽  
Mohammad Motalab ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Compressive Stress ◽  
Heat Sink ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Excellent Correlation ◽  
Printed Circuit ◽  
Stress Changes ◽  
Die Stress ◽  
Test Chips

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general “rule of thumb,” approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to − 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

In-Plane Packaging Stress Measurements Through Piezoresistive Sensors

2002 ◽  
Vol 124 (2) ◽  
pp. 115-121 ◽  
Author(s):  
Ben-Je Lwo ◽  
Tung-Sheng Chen ◽  
Ching-Hsing Kao ◽  
Yu-Lin Lin
Keyword(s):  
Thermal Stresses ◽  
Temperature Sensors ◽  
Internal Stresses ◽  
Microelectronic Packaging ◽  
Stress Measurements ◽  
Piezoresistive Sensors ◽  
Stress Sensors ◽  
Induced Stresses ◽  
Packaging Structure ◽  
Test Chips

In our previous works, the piezoresistive sensors have been demonstrated to be accurate and efficient tools for stress measurements in microelectronic packaging. In this study, we first designed test chips with piezoresistive stress sensors, temperature sensors as well as heats, and the test wafers were next manufactured through commercialized IC processes. Piezoresistive sensors on silicon strips, which were cut directly from silicon wafers at a specific angle, were then calibrated, and highly consistent piezoresistive coefficients were extracted at various wafer sites so that both normal and shear stress on the test chips can be measured. Finally, we packaged the test chips into 100-pin PQFP structures with different batches and measured internal stresses on the test chips inside the packaging. After measuring packaging induced stresses as well as thermal stresses on several batches of PQFPs, it was found that the normal stress diversities were obvious from different batches of the packaging structure, and the shearing stresses were approximately zero in all of the PQFPs at different chip site.

Characterization of Die Stresses in Plastic Packages Subjected to Moisture and Thermal Exposures

2015 ◽  
Author(s):  
Quang Nguyen ◽  
M. Kaysar Rahim ◽  
Jordan C. Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger
Keyword(s):  
Normal Stress ◽  
Shear Stresses ◽  
Stress Distributions ◽  
Long Term Storage ◽  
Plastic Packages ◽  
Stress Changes ◽  
Die Stress ◽  
Test Chips ◽  
Term Storage

Stress sensing test chips are a powerful tool for measuring in-situ stresses in electronic packages. In this study, we have applied (111) silicon test chips to perform a variety of measurements of die stresses in plastic packages. In particular, stresses were characterized in 240 pin Quad Flat Packs (QFPs) subjected to various thermal and moisture loadings. The utilized 10 × 10 mm sensor chips incorporated optimized eight-element piezoresistive rosettes that were capable of measuring the complete state of stress at the die surface (including the interfacial shear stresses). The fabricated test chips were initially used to measure die stresses in the QFPs after molding and post mold bake. Measurement results were correlated with finite element simulations of the molding process. Subsequently, the effects of thermal cycling on the measured die stress distributions for selected packages were investigated. After these initial measurements, the samples were stored at room temperature and ambient humidity for 17 years. The samples were then re-measured after this long term storage to evaluate the degree of die stress relaxation that had occurred. Several packages were then exposed to a harsh high temperature and high humidity environment (85 C, 85% RH) for various time durations, and allowed to absorb moisture. The die stresses at several locations were characterized as a function of time during the hygrothermal exposure. The weight variations in each sample were also measured during the 85/85 exposure to gauge the moisture uptake, and reversibility tests were conducted to see whether the effects of moisture uptake were permanent. Using these measurements and numerical simulations, valuable insight has been gained on moisture induced failure phenomena in plastic packages. Good agreement was found between the predicted and measured die normal stress distributions occurring after molding of the QFP. The magnitudes of the in-plane normal and shear stresses were found to have decreased by up to 30% after moderate levels of thermal cycling. After long term storage, the experimental measurements showed that the die normal stresses in the QFPs relaxed significantly (up to 40%), while the die shear stresses exhibited only small variations. In addition, the 85/85 hygrothermal exposures had strong effects, generating tensile die normal stress changes of up to 130 MPa. Upon fully redrying in reversibility tests, it was observed that the moisture-induced normal stress changes were not recovered. Good correlations were observed between the variations of sample weight (increases in moisture content) and the variations of the die normal and shear stress changes.

Measurement of Microprocessor Die Stress due to Thermal Cycling, Power Cycling, and Second Level Assembly

2013 ◽  
Author(s):  
Jordan C. Roberts ◽  
Mohammad Motalab ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Power ◽  
Three Dimensional ◽  
Power Cycling ◽  
Die Stress ◽  
Test Chips ◽  
Resistance Data ◽  
Critical Locations

In the current work, we have extended our past studies on Flip Chip Ceramic Ball Grid Array (FC-BGA) microprocessor packaging configurations to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings. Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time.

Sign in / Sign up

Export Citation Format

Share Document