In-Plane Packaging Stress Measurements Through Piezoresistive Sensors

2002 ◽  
Vol 124 (2) ◽  
pp. 115-121 ◽  
Author(s):  
Ben-Je Lwo ◽  
Tung-Sheng Chen ◽  
Ching-Hsing Kao ◽  
Yu-Lin Lin
Keyword(s):  
Thermal Stresses ◽  
Temperature Sensors ◽  
Internal Stresses ◽  
Microelectronic Packaging ◽  
Stress Measurements ◽  
Piezoresistive Sensors ◽  
Stress Sensors ◽  
Induced Stresses ◽  
Packaging Structure ◽  
Test Chips

In our previous works, the piezoresistive sensors have been demonstrated to be accurate and efficient tools for stress measurements in microelectronic packaging. In this study, we first designed test chips with piezoresistive stress sensors, temperature sensors as well as heats, and the test wafers were next manufactured through commercialized IC processes. Piezoresistive sensors on silicon strips, which were cut directly from silicon wafers at a specific angle, were then calibrated, and highly consistent piezoresistive coefficients were extracted at various wafer sites so that both normal and shear stress on the test chips can be measured. Finally, we packaged the test chips into 100-pin PQFP structures with different batches and measured internal stresses on the test chips inside the packaging. After measuring packaging induced stresses as well as thermal stresses on several batches of PQFPs, it was found that the normal stress diversities were obvious from different batches of the packaging structure, and the shearing stresses were approximately zero in all of the PQFPs at different chip site.

In Situ Chip Stress Extractions for LFBGA Packages Through Piezoresistive Sensors

2009 ◽  
Vol 131 (3) ◽  
Author(s):  
Ben-Je Lwo ◽  
Jeng-Shian Su ◽  
Hsien Chung
Keyword(s):  
Stress Measurements ◽  
Piezoresistive Sensors ◽  
Stress Sensors ◽  
Compressive Stresses ◽  
Fine Pitch ◽  
Low Profile ◽  
Quad Flat Package ◽  
On Chip ◽  
Test Chips

Piezoresistive sensors have been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, test chips with piezoresistive stress sensors, diode temperature sensors as well as heaters were first designed, fabricated, and calibrated. We next packaged the test chips into low profile, fine pitch ball grid array (LFBGA) packaging with 196 balls and measured the stresses on chip surfaces inside the packaging. After measuring the packaging induced stress as well as the stress under stable environmental temperature rises, it was found that compressive stresses were obtained at room temperature, and the stresses were relaxed as temperature went up at a rate between 0.45 MPa/°C and 0.60 MPa/°C. For thermo-stress experiments, the temperatures on chip surfaces at different power levels were measured, and compressive chip stresses were first extracted. As the chip power increased, the compressive stresses became tensions. Since the LFBGA structure is thinner with higher packaging efficiency, different results from our earlier plastic quad flat package stress measurements were observed and discussed. In addition, the final comparisons between the experimental data and the finite element simulations show good consistency.

On the Study of Piezoresistive Stress Sensors for Microelectronic Packaging

2000 ◽  
Vol 124 (1) ◽  
pp. 22-26 ◽  
Author(s):  
Ben-Je Lwo ◽  
Ching-Hsing Kao ◽  
Tung-Sheng Chen ◽  
Yao-Shing Chen
Keyword(s):  
Input Power ◽  
Microelectronic Packaging ◽  
Piezoresistive Sensors ◽  
Four Point Bending ◽  
Stress Sensors ◽  
Linear Relationships ◽  
Study Test ◽  
As Stress ◽  
Test Chips ◽  
P Type

Stress measurements in microelectronic packaging through piezoresistive sensors take the advantage of both in-situ and nondestructive. In this study, test chips with both p-type and n-type piezoresistive stress sensors, as well as a heat source, were first designed, then manufactured by a commercialized foundry so that the uniformity of the test chips was expected. Both temperature and stress calibrations were next performed through a special designed MQFP (Metal Quad Flat Package) and four-point bending (4PB) structure, respectively. Measurements of stresses which are produced due to both manufacturing process and thermal effects on the test chips were finally executed, and approximately linear relationships were observed between stress and temperature as well as stress and input power. It is concluded that n-type piezoresistive stress sensors are able to extract stress in microelectronic packaging with good accuracy.

Piezoresistive Stress Sensors for Structural Analysis of Electronic Packages

1991 ◽  
Vol 113 (3) ◽  
pp. 203-215 ◽  
Author(s):  
D. A. Bittle ◽  
J. C. Suhling ◽  
R. E. Beaty ◽  
R. C. Jaeger ◽  
R. W. Johnson
Keyword(s):  
Integrated Circuit ◽  
Structural Reliability ◽  
Lattice Structure ◽  
Three Dimensional ◽  
Electronic Packages ◽  
Cubic Symmetry ◽  
Piezoresistive Sensors ◽  
Stress Sensors ◽  
Die Stress ◽  
Test Chips

Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the theory of conduction in piezoresistive materials is reviewed and the basic equations applicable to the design of stress sensors on test chips are presented. General expressions are obtained for the stress-induced resistance changes which occur in arbitrarily oriented one-dimensional filamentary conductors fabricated out of crystals with cubic symmetry and diamond lattice structure. These relations are then applied to obtain basic results for stressed in-plane resistors fabricated into the surface of (100) and (111) oriented silicon wafers. Sensor rosettes developed by previous researchers for each of these wafer orientations are reviewed and more powerful rosettes are presented along with the equations needed for their successful application. In particular, a new sensor rosette fabricated on (111) silicon is presented which can measure the complete three-dimensional stress state at points on the surface of a die

Measurement of Stress and Delamination in Flip Chip on Laminate Assemblies

2003 ◽  
Author(s):  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
D. Scott Copeland ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Flip Chip ◽  
Acoustic Microscopy ◽  
Valuable Insight ◽  
Stress Distributions ◽  
Environmental Testing ◽  
Stress Measurements ◽  
Piezoresistive Sensors ◽  
Die Stress ◽  
Test Chips ◽  
Stress Variations

Mechanical stress distributions in packaged silicon die that have resulted during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, an overview of recent measurements made in flip chip on laminate assemblies with (111) silicon test chips is presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. The experimental stress measurements in the flip chip samples were then correlated with finite element predictions for the tested configurations. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from −40 to +150°C. Finally the stress variations occurring during thermal cycling from −40 to +125°C have been characterized. These measurements have been correlated with the delaminations occurring at the die passivation to underfill interface measured using C-mode Scanning Acoustic Microscopy (C-SAM). Using the measurements and numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

The Control Of Intrinsic Stresses In Cvd Diamond Films With Multistep Processing

1995 ◽  
Vol 416 ◽  
Author(s):  
S. Nijhawan ◽  
S. M. Jankovsky ◽  
B. W. Sheldon
Keyword(s):  
Thermal Stresses ◽  
Microwave Plasma ◽  
Diamond Films ◽  
Annealing Treatment ◽  
Chemical Vapor ◽  
Deposition Process ◽  
Internal Stresses ◽  
Tensile Stresses ◽  
Si Substrates

ABSTRACTThe role of intrinsic stresses in diamond films is examined. The films were deposited on (100) Si substrates by microwave plasma-enhanced chemical vapor deposition. The total internal stresses (thermal and intrinsic) were measured at room temperature with the bending plate method. The thermal stresses are compressive and arise due to the mismatch in thermal expansion coefficient of film and substrate. The intinsic stresses were tensile and evolved during the deposition process. These stresses increased with increasing deposition time. A 12 hour intermediate annealing treatment was found to reduce the tensile stresses considerably. The annealing treatment is most effective when the diamond crystallites are undergoing impingement and coalescence. This is consistent with the theory that the maximum tensile stresses are associated with grain boundary energetics.

Chip-on-Beam and Hydrostatic Calibration of the Piezoresistive Coefficients on (111) Silicon

2007 ◽  
Author(s):  
Chun-Hyung Cho ◽  
Richard C. Jaeger ◽  
Jeffrey C. Suhling ◽  
M. Kaysar Rahim
Keyword(s):  
Pressure Coefficient ◽  
Experimental Methods ◽  
Temperature Dependent ◽  
Pressure Coefficients ◽  
Stress Sensors ◽  
Wide Range ◽  
Complete Set ◽  
Stress Sensing ◽  
Test Chips ◽  
P Type

Stress sensing test chips are used to investigate die stresses arising from assembly and packaging operations. The chips incorporate resistor or transistor sensing elements that are able to measure stresses via the observation of the changes in their resistivity/mobility. The piezoresistive behavior of such sensors is characterized by three piezoresistive (pi) coefficients, which are electro-mechanical material constants. Stress sensors fabricated on the surface of the (111) silicon wafers offer the advantage of being able to measure the complete stress state compared to such sensors fabricated on the (100) silicon. However, complete calibration of the three independent piezoresistive coefficients is more difficult and one approach utilizes hydrostatic measurement of the silicon “pressure” coefficients. We are interested in stress measurements over a very broad range of temperatures, and this paper present the experimental methods and results for hydrostatic measurements of the pressure coefficient of both n- and p-type silicon over a wide range of temperatures and then uses the results to provide a complete set of temperature dependent piezoresisitive coefficients for the (111) silicon.

Characterization of the Piezoresistive Coefficients of (100) Silicon From −150 to +125C

2007 ◽  
Author(s):  
Chun-Hyung Cho ◽  
Richard C. Jaeger ◽  
Jeffrey C. Suhling
Keyword(s):  
Integrated Circuit ◽  
Carrier Mobility ◽  
Limited Data ◽  
Experimental Calibration ◽  
Four Point Bending ◽  
Stress Sensors ◽  
Stress Sensing ◽  
Test Chips ◽  
Crystallographic Axes

Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. The test chips incorporate resistor or transistor sensing elements that are able to measure stresses by observing the changes in their resistivity or carrier mobility. This piezoresistive behavior of such sensors is characterized by three piezoresistive coefficients, which are electro-mechanical material constants. We are interested in stress characterization over a very broad range of temperatures. However, the literature provides limited data over the desired range, and even the data at room temperature, exhibit wide discrepancies in magnitude as well as sign. This work focuses on an extensive experimental study of the temperature dependence of the piezoresistive coefficients, π11, π12, and π44, for both p- and n-type silicon. In order to minimize errors associated with misalignment with the crystallographic axes on (100) silicon wafers, anisotropic wet etching was used in this work to accurately locate the axes. A special four-point bending apparatus has been constructed and integrated into an environmental chamber capable of temperatures from −155 to +300°C. Experimental calibration results for the piezoresistive coefficients as a function of temperature from −150°C to +125°C are presented and compared and contrasted with existing values from literature. Measurements were performed using stress sensors fabricated on (100) silicon mounted on PCB material including both die-on-beam and strip-on-beam mounting techniques. Four-point bending (4PB) was used to generate the required stress, and finite element simulations have been used to determine the actual states of stress in the silicon material.

Comparison of Thermal and Stress Analysis Results for a High Voltage Module Using FEA and a Quick Parametric Analysis Tool

2018 ◽  
Author(s):  
L. M. Boteler ◽  
S. M. Miner
Keyword(s):  
Stress Analysis ◽  
High Voltage ◽  
Parametric Analysis ◽  
Thermal Stresses ◽  
Analysis Tool ◽  
Element Analysis ◽  
Module Design ◽  
Fast Running ◽  
Packaging Structure ◽  
Low Order

A low order fast running parametric analysis tool, ParaPower, was used to arrive at the design for a novel high voltage module. The low order model used a 3D nodal network to calculate device temperatures and thermal stresses. The model assumed heat flux generated near the top surface of each device which is then conducted through the packaging structure and removed by convection. The temperature distribution is used to calculate thermal stresses throughout the package. This co-design modeling tool, developed for rectilinear geometries, allowed a rapid evaluation of the package temperatures and CTE induced stresses throughout the design space. However, once the final design configuration was determined a detailed finite element analysis was performed to validate the design. This paper compares the results obtained using ParaPower to the FEA, demonstrating the usefulness of the parametric analysis tool. Results for both temperature and CTE induced stress are compared. Two different stress models are evaluated. One based on the more traditional planar module design, which assumes a substantial substrate or heat spreader on which the module is assembled. The other model is less restrictive, eliminating the requirement for a substrate. The FEA modeling was performed using SolidWorks beginning with a thermal analysis followed by a stress analysis based on the temperature solution. Both the values and the trends of the temperatures and stresses were evaluated. The temperature results agreed to within 3.2°C. The trends and sign of the stresses were correctly predicted, but the magnitudes were not. One of the significant advantages of ParaPower is the speed of the computation. The run time for the parametric analysis was roughly two orders of magnitude faster than the FEA. This made it possible to build the model and complete the parametric analysis of roughly 500 runs in less than a day.

Finite Element Simulation of Steel Quench Distortion- Parametric Analysis of Processing Variables

2012 ◽  
Vol 1485 ◽  
pp. 29-34 ◽  
Author(s):  
F. A. García-Pastor ◽  
R.D. López-García ◽  
E. Alfaro-López ◽  
M. J. Castro-Román
Keyword(s):  
Finite Element ◽  
Martensitic Transformation ◽  
Internal Stress ◽  
Thermal Stresses ◽  
Stress Fields ◽  
Leaf Spring ◽  
Internal Stresses ◽  
Processing Temperature ◽  
Fe Model ◽  
Slow Cooling

ABSTRACTSteel quenching from the austenite region is a widely used industrial process to increase strength and hardness through the martensitic transformation. It is well known, however, that it is very likely that macroscopic distortion occurs during the quenching process. This distortion is caused by the rapidly varying internal stress fields, which may change sign between tension and compression several times during quenching. If the maximum internal stress is greater than the yield stress at given processing temperature, plastic deformation will occur and, depending on its magnitude, macroscopic distortion may become apparent.The complex interaction between thermal contraction and the expansion resulting from the martensitic transformation is behind the sign changes in the internal stress fields. Variations in the steel composition and cooling rate will result in a number of different paths, which the internal stresses will follow during processing. Depending on the route followed, the martensitic transformation may hinder the thermal stresses evolution to the point where the stress fields throughout the component may actually be reverted. A different path may support the thermal stresses evolution further increasing their magnitude. The cross-sectional area also affects the internal stresses magnitude, since smaller areas will have further trouble to accommodate stress, thus increasing the distortion. Additionally, the bainitic transformation occurring during relatively slow cooling rates may have an important effect in the final stress field state.A finite-element (FE) model of steel quenching has been developed in the DEFORM 3D simulation environment. This model has taken into account the kinetics of both austenite-bainite and austenite-martensite transformations in a simplified leaf spring geometry. The results are discussed in terms of the optimal processing parameters obtained by the simulation against the limitations in current industrial practice.

Thermal Control of Interfaces for Microelectronic Packaging

1998 ◽  
Vol 515 ◽  
Author(s):  
E. E. Marotta ◽  
B. Hana
Keyword(s):  
Thermal Performance ◽  
Flip Chip ◽  
Printed Circuit Boards ◽  
Thermal Stresses ◽  
Experimental Studies ◽  
Thermal Control ◽  
Thermal Contact Conductance ◽  
Microelectronic Packaging ◽  
Chip Technology ◽  
Operating Temperatures

ABSTRACTThe continuous miniaturization of electronic devices places an ever-increasing importance on the thermal management of electronic systems and its subcomponents. The increased power densities and heat generation, due to the miniaturization of the device line features, may lead to higher operating temperatures and greater warpage between the silicon device and its organic carrier. The higher operating temperature may result from the degradation of the overall thermal performance. These additive effects will also lead to an increasing number of thermally induced failures, which will be further magnified when future microelectronic packaging incorporates flip-chip technology.The higher operating temperatures within microelectronic systems result from inadequate dissipation of the heat generated, while the warpage effect is caused by the mismatch between the thermal coefficients of expansion (ICE) induced by thermal stresses. Often these high temperatures result from the thermal resistance between subcomponents, such as between the contacting surfaces of laminated printed circuit boards, device/epoxy cement and heat spreader (i.e., finned heat sink or heat pipe), and any other metallic or non-metallic interstitial material employed between contacting interfaces.Published experimental data of potential coatings, adhesives, and elastomeric gaskets is presented that can improve the thermal contact conductance of contacting surfaces within microelectronic systems. In addition, recommendations for future analytical and experimental studies of the mnechanistic principles, which control thermal performance of interstitial materials, are discussed for non-uniform pressure distribution.

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