Modeling and experimentation of creep-fatigue and failure of low-profile quad flat package under thermal cycle

An experimental investigation and numerical modeling using multiphysics finite element method were performed to study the thermal failure mechanism of low-profile quad flat package solder joints of memory module due to low-cycle fatigue. The strain, stress, and number of cycles to failure have been calculated according to a strain life Coffin–Manson and energy-based Morrow fatigue models. Scanning electron microscopy imaging at the end of thermal cycle was used to evaluate the damage initiation and propagation. The effect of the solder volume on fatigue life of solder joints was discussed. Through analyses of theoretical results and experimental data on fatigue life, cracks initiation and propagation have been highlighted and their possible causes have been discussed.

MODIFIKASI MESIN TRIM FORM PADA PROSES PENGEMASAN INTEGRATED CIRCUIT UNTUK PENURUNAN DAMAGED LEAD

Proses pengemasan Integrated Circuit (IC) pada kemasan Low Profile Quad Flat Package (LQFP) membutuhkan mesin trim form untuk pemotongan dambar dan pembentukan kaki IC sebelum dipisahkan dari lead frame. Salah satu urutan proses pada mesin trim form adalah offload yaitu penempatan IC ke dalam tray dengan modul pick and place termasuk didalamnya turn table dengan pergerakan buka tutup untuk menyesuaikan jarak antar kolom dari leadframe sebelum dipindahkan ke tray. Pergerakan buka tutup dari turn table ini berpengaruh terhadap cacat produksi damaged lead. Modifikasi ditujukan untuk deteksi dini misalignment sehingga mesin dapat berhenti otomatis dan mengurangi cacat produksi melalui penambahan dua sensor proximity pada turn table. Hasil penelitian menunjukkan penurunan error pada turn table sebesar 88% dan assembly yield mencapai 99.985% atau terjadi peningkatan sebesar 0.07%.

Influence of Interfacial Intermetallic Growth on the Mechanical Properties of Sn-37Pb Solder Joints under Extreme Temperature Thermal Shock

Solder joints in thermally uncontrolled microelectronic assemblies have to be exposed to extreme temperature environments during deep space exploration. In this study, extreme temperature thermal shock test from −196 °C to 150 °C was performed on quad flat package (QFP) assembled with Sn-37Pb solder joints to investigate the evolution and growth behavior of interfacial intermetallic compounds (IMCs) and their effect on the pull strength and fracture behavior of Sn-37Pb solder joints under extreme temperature environment. Both the scallop-type (Cu, Ni)6Sn5 IMCs at the Cu lead side and the needle-type (Ni, Cu)3Sn4 IMCs at the Ni-P layer side changed to plane-type IMCs during extreme temperature thermal shock. A thin layer of Cu3Sn IMCs was formed between the Cu lead and (Cu, Ni)6Sn5 IMC layer after 150 cycles. The growth of the interfacial IMCs at the lead side and the Ni-P layer side was dominated by bulk diffusion and grain-boundary diffusion, respectively. The pull strength was reduced about 31.54% after 300 cycles. With increasing thermal shock cycles, the fracture mechanism changed from ductile fracture to mixed ductile–brittle fracture, which can be attributed to the thickening of the interfacial IMCs, and the stress concentration near the interface caused by interfacial IMC growth.

Novel IC Device Repackaging for SIL and Backside Analysis Capability

A novel approach for solid immersion lens (SIL) assisted imaging and backside analysis of chip-on-board devices is presented. The procedure relies on complete die extraction from its original package, and repackage into a FA-friendly Plastic Quad-Flat Package (PQFP) chip carrier with inverted mold configuration, which enables access to the backside of the die through grinding/polishing or other methods. This procedure also relies on complementing use of device-specific DUT boards with generic arrangement of I/O, ground and power domains, coupled with a bench-test board equipped with the same pin-out configuration and a custom carrier built specifically for these DUT boards. This generic approach broadens the use of this solution to an entire family of devices and offers a balance of test capability leading to fault localization success and cost control.