Thermal Reliability of Low-Cost High-Power LED Package Module Under WHTOL Test

Author(s):  
C. H. Chen ◽  
W. L. Tsai ◽  
C. Y. Tang ◽  
M. Y. Tsai

The LED issues, associated with high cost, high junction temperature, low luminous efficiency, and low reliability, have to be solved before gaining more market penetration. With special features of low-junction-temperature and low-cost design, COP (Chip-on-Plate) LED package modules with and without phosphors are evaluated in terms of their thermal resistance and reliability under wet high temperature operation life (WHTOL) test. The WHTOL test is with the condition of 85°C/85% RH and 350mA of forward current for 1008 hrs, specified in JESD22 Method A101-B. First of all, the thermal behaviors of the COP package module are investigated by experimental measurement, and a computational fluid dynamics approach. The reliability under WHTOL test is then carried out. The results show that all COP package modules with phosphors in the silicone encapsulant failed after 309 hrs at WHTOL test, but all those without phosphors passed for 1008 hrs. The failure sites are located at aluminum wire debonding to the chip and copper pads of the substrate. However, the aluminum wire bonding of the COP package modules are replaced to gold wire bonding, then all COP package modules with and without phosphors pass for 1008 hrs. For the passing package modules, their thermal resistances are found to increase more than two fold after 1008 hrs of the WHTOL test from 41°C/W to 87.1°C/W. This is due to the thermal conductivity decreasing in the die attach and thermal grease and the contact resistance increasing after the moisture absorption. Moreover, for the thermal behavior of the COP package modules under the natural and forced convections in the WHTOL test, the results show that there exists the difference of 17°C/W in the junction-to-air thermal resistances, which might result in different reliability data. In addition, it is also indicated that the junction-to-air thermal resistances are very sensitive to the flow conditions of the chamber, but not for junction-to-aluminum substrate and junction-to-heat sink thermal resistances. Therefore, the standard test of the WHTOL should specify flow conditions in the test chamber.

2012 ◽  
Vol 2012 (CICMT) ◽  
pp. 000334-000338
Author(s):  
Jens Müller ◽  
Thomas Mache ◽  
Torsten Thelemann

Electroless plating on silver is a low cost alternative to printing of mixed metals or pure gold paste systems on LTCC. It overcomes the necessity to have material transitions from inner to outer layers or from conductor lines to wire bonding- or solder-pads. Since no commercial process and material set for silver thick film conductors has been available on the market a proprietary Ni/Pd/Au coating technology was developed for the use on silver inks for LTCC and Al2O3-ceramic as a base for both soldering and wire bonding. The work included the screening of different chemicals as well as several silver paste systems from two commercial vendors. Conductor adhesion, plating layer thicknesses, plating accuracy, (lead free) solderability and gold wire-bondability were assessed to optimize the process. Layers of about 5 microns Ni, (0.1 to 0.3) microns Pd and (0.05 to 0.15) microns Au were electrolessly deposited. The developed Ni-Pd-Au finish is an economical alternative with only about a quarter of the cost compared to the conventional use of silver, silver / palladium and gold compounds for ceramic substrates. This technology allows coating of the structures down to a fine pad size of 200×200 microns and a minimum line width of 100 microns, without reducing the adhesion mechanism between thick-film metallization and ceramic substrate. By covering of pure conductors with high temperature glass or dielectrics, further material saving is possible. Besides, the process offers also very good coating of structures in cavities.


2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001948-001966 ◽  
Author(s):  
James J. Wang

Inductors directly on-chip was designed, processed and tested. Combining thick, electroplated gold used to produce LCD driver ICs plus gold wire bonding, toroidal inductors are formed directly on top of ICs. Both processes are production ready. One layouts inductor line segments on top of ICs and then complete loops using gold wire bonds at packaging. Two, 4, 8 or 16 toroids will fit inside thin QFN package. Cost to integrate 2 or more inductors is less than buying 0402 chip inductors and then soldering SMT components around ICs. Integrating inductors shrinks PCB board and allows IC design of filters, LC oscillator, EM noise suppression or ESD protection circuits. On-chip 4nH to 2000nH inductors is practical today. Choosing the magnetic core material and selecting the number of loops/turns, designers can integrate different inductors on top of an existing IC. Custom, ultra-tiny magnetic cores are produced from same magnetic materials that are inside discrete inductors or transformers. 50nH to 500nH inductors with Q comparable to chip inductors are possible for MHz frequency ranges by selecting ferrite core. Using high permeability permalloy, one produces 200nH to 2000nH inductors or transformers directly on-chip. Flexibility is another advantage of on-chip Gold InductorsTM. By adjusting loop heights during wire bonding, one can adjust inductance value +- 100%. By laying out both primary and secondary coils around magnetic core, designers can choose to integrate transformer or inductors. Low cost, production processes, control with IC design, plus flexibility, one can begin to design and produce on-chip filters and transformers; achieving smaller electronics.


2013 ◽  
Vol 2013 (1) ◽  
pp. 000336-000340
Author(s):  
Kong Weng Lee ◽  
Lei Xu ◽  
Jay Skidmore

The trends of increasing demand of higher power laser devices with increased current capacity and total package cost reduction to improve dollars per watt of laser output power have resulted in the need for alternatives to traditional gold wirebonds on gold-plated substrates. Copper and aluminum wires are considered to be the leading candidates due to their vast reliability database in the semiconductor industry and cost advantages. Room temperature (25°C) wirebonding with a robust process window and high yield is required for high-volume, low-cost applications. The wirebonds must also meet or exceed the stringent reliability requirements of 1000 hours at 85°C/85%RH damp heat (DH) and 1000 hrs at 175°C high temperature storage (HTS) testing. In this study, 10 mils round thick copper and aluminum wire bonding has been successfully developed at room temperature with no intermetallic failure or void formation at the Al/Au and Cu/Au interfaces after 1000 hours of DH and HTS testing. Further investigation with corrosion-resistant Al wire shows excellent pull strength and wire shear per Mil-Std 883 after 2000 hours of DH and HTS testing with no evidence of void formation at the Al/Au interface. The thickness of the Au-Al intermetallic is found to be minimal at ∼4um after 1000 hours of HTS testing. This study has demonstrated that both thick copper and aluminum wire are capable of wire bonding at room temperature to function as a reliable interconnect with improved product performance and low cost.


2011 ◽  
Vol 2011 (1) ◽  
pp. 000589-000599
Author(s):  
Tu Anh Tran ◽  
Varughese Mathew ◽  
Harold Downey

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. More reliable intermetallic systems have been proposed that change the wire material and/or the bond pad metallization. An alternative wire material to gold, copper, has many benefits including low cost, high electrical and thermal conductivities and excellent reliability with aluminum pad metallization. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on evaluating Au and Cu wire bonding on low-K-copper wafers having two types of bonding surfaces, the conventional aluminum pad and aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold. Ni thickness ranging from 1μm to 3μm was evaluated. Defects on as-plated Ni/Pd/Au bond pads such as color difference and surface roughness were determined to be due to nodule growth and plating non-uniformity. Wire bonded strip-level thermal aging was conducted to compare the high-temperature performance of the four interconnect types. Packages underwent extensive reliability stress conditions. Cross-sectioning through the ball bonds was also conducted to examine the welding region between the ball bond and bond pad. Defects in plating and wire bonding processes causing package reliability failures were identified. Recommendations for plating and wire bonding processes were derived to ensure high quality and reliable interconnect exceeding AEC grade 0 requirements.


2021 ◽  
pp. 1-7
Author(s):  
Diane Stephenson ◽  
Reham Badawy ◽  
Soania Mathur ◽  
Maria Tome ◽  
Lynn Rochester

The burden of Parkinson’s disease (PD) continues to grow at an unsustainable pace particularly given that it now represents the fastest growing brain disease. Despite seminal discoveries in genetics and pathogenesis, people living with PD oftentimes wait years to obtain an accurate diagnosis and have no way to know their own prognostic fate once they do learn they have the disease. Currently, there is no objective biomarker to measure the onset, progression, and severity of PD along the disease continuum. Without such tools, the effectiveness of any given treatment, experimental or conventional cannot be measured. Such tools are urgently needed now more than ever given the rich number of new candidate therapies in the pipeline. Over the last decade, millions of dollars have been directed to identify biomarkers to inform progression of PD typically using molecular, fluid or imaging modalities). These efforts have produced novel insights in our understanding of PD including mechanistic targets, disease subtypes and imaging biomarkers. While we have learned a lot along the way, implementation of robust disease progression biomarkers as tools for quantifying changes in disease status or severity remains elusive. Biomarkers have improved health outcomes and led to accelerated drug approvals in key areas of unmet need such as oncology. Quantitative biomarker measures such as HbA1c a standard test for the monitoring of diabetes has impacted patient care and management, both for the healthcare professionals and the patient community. Such advances accelerate opportunities for early intervention including prevention of disease in high-risk individuals. In PD, progression markers are needed at all stages of the disease in order to catalyze drug development—this allows interventions aimed to halt or slow disease progression, very early, but also facilitates symptomatic treatments at moderate stages of the disease. Recently, attention has turned to the role of digital health technologies to complement the traditional modalities as they are relatively low cost, objective and scalable. Success in this endeavor would be transformative for clinical research and therapeutic development. Consequently, significant investment has led to a number of collaborative efforts to identify and validate suitable digital biomarkers of disease progression.


Author(s):  
S.L. Khoury ◽  
D.J. Burkhard ◽  
D.P. Galloway ◽  
T.A. Scharr

1999 ◽  
Vol 22 (1) ◽  
pp. 7-15 ◽  
Author(s):  
R.W. Johnson ◽  
M.J. Palmer ◽  
M.J. Bozack ◽  
T. Isaacs-Smith

2015 ◽  
Vol 137 (1) ◽  
Author(s):  
Fuliang Wang ◽  
Dengke Fan

A wire clamp is used to grip a gold wire with in 1–2 ms during thermosonic wire bonding. Modern wire bonders require faster and larger opening wire clamps. In order to simplify the design process and find the key parameters affecting the opening of wire clamps, a model analysis based on energy conservation was developed. The relation between geometric parameters and the amplification ratio was obtained. A finite element (FE) model was also developed in order to calculate the amplification ratio and natural frequency. Experiments were carried out in order to confirm the results of these models. Model studies show that the arm length was the major factor affecting the opening of the wire clamp.


2011 ◽  
Vol 1335 ◽  
Author(s):  
Romain Cauchois ◽  
Mohamed Saadaoui ◽  
Karim Inal ◽  
Beatrice Dubois-Bonvalot ◽  
Jean-Christophe Fidalgo

ABSTRACTIn this paper, silver nanoparticles with a mean diameter of 40 nm are studied for future applications in microelectronic devices. The enhanced diffusivity of nanoparticles is exploited to fabricate electrical interconnects at low temperature. Sintering condition has been tuned to tailor the grain size so that electrical resistivity can be lowered down to 3.4 μOhm∙cm. In this study, a {111}-textured gold thin film has been used to increase diffusion routes. The combined effects of the substrate crystalline orientation and the sintering condition have been demonstrated to have a significant impact on microstructures. In particular, a {111} fiber texture is developed above 300°C in printed silver only if the underlying film exhibits a preferential orientation. This condition appeared as essential for the efficiency of the gold wire-bonding process step. Thus, inkjet-printed interconnects show a prospective potential compared to conventional subtractive technique and offers new opportunities for low cost metallization in electronics packaging.


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