Thermal Cycling Guidelines for Automotive, Computer, Portable, and Implantable Medical Device Applications

2000 ◽  
Author(s):  
Rajiv Raghunathan ◽  
Raghuram V. Pucha ◽  
Suresh K. Sitaraman

Abstract The objective of this work is to develop qualification guidelines for Flip-Chip on Board (FCOB) and Flip Chip Chip-Scale Packages (FCCSP) used in implantable medical devices, automotive applications, computer applications and portables, taking into consideration the thermal history associated with the field conditions. The accumulated equivalent inelastic strain per cycle and the maximum strain energy density have been used as damage parameters to correlate solder fatigue damage during field use and thermal cycling. The component assembly process mechanics, the time and temperature-dependent material behavior, and the critical geometric features of the assembly have been taken into consideration for developing the comprehensive virtual qualification methodology.

1993 ◽  
Vol 115 (1) ◽  
pp. 16-21 ◽  
Author(s):  
V. Sarihan

Solder is being extensively used in electronic packages for both electrical and mechanical connection. Solder joints are subjected to severe operating conditions and hence their reliability is very critical for the packages. Simulation is very effective for understanding, predicting and design improvement of electronic packages where solder is the prime joiner, however all the material response complexities of solder over the temperature regime it is subjected to should be modelled. Solder in electronic components very often operates at 0.6 to 0.8 times it’s melting point. In this regime the time dependent material response (creep and stress relaxation) is very significant and can no longer be ignored. Also the plastic and creep responses of solder alloys have a very strong dependence on temperature. A nonlinear finite element based methodology has been developed for simulation of solder alloy over its full regime of material behavior, also accounting for the strong temperature dependence. This includes elastic, time independent plastic, and time dependent viscoplastic response. The methodology has been used for predicting the response of a flip chip with 95Pb5 percent Sn peripheral bumps subjected to thermal cycling. Correlation is observed between the location of failure in the bump and the maximum inelastic strain. The importance of doing a multicycle simulation is demonstrated and a direction is indicated for the bump size modification for flip chip bump design improvements for greater reliability.


Author(s):  
M. Kaysar Rahim ◽  
Jordan Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete three-dimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 × 5 mm perimeter bumped die were assembled on FR-406 substrates. Three different thermal cycling temperature profiles were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.


Author(s):  
Chang Lin ◽  
Jeffrey C. Suhling ◽  
Pradeep Lall

Microelectronic encapsulants exhibit evolving properties that change significantly with environmental exposures such as isothermal aging and thermal cycling. Such aging effects are exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In this work, measurements of material behavior changes occurring in flip chip underfill encapsulants exposed to isothermal aging have been performed. A novel method has been developed to fabricate freestanding underfill uniaxial test specimens so that they accurately reflect the encapsulant layer present in flip chip assemblies. Using the developed specimen preparation procedure, isothermal aging effects have been characterized at several elevated temperatures (+ 80, +100, + 125, and +150 °C). Samples have been aged at the four temperatures for periods up to 6 months. Stress-strain and creep tests have been performed on non-aged and aged samples, and the changes in mechanical behavior have been recorded for the various aging temperatures and durations of isothermal exposure. Empirical models have been developed to predict the evolution of the material properties (modulus, strength) and the creep strain rate as a function of temperature, aging time, and aging temperature. The evaluated underfill illustrated softening behavior at temperatures exceeding 100 °C, although the documented Tg ranged from 130–150 °C. The obtained results showed an obvious enhancement of the underfill mechanical properties as a function of the aging temperature and aging time. Both the effective elastic modulus (initial slope) and ultimate tensile strength (highest stress before failure) increase monotonically with the amount of isothermal aging or aging temperature, regardless of whether the aging temperature is below, at, or above the Tg of the material. From the creep results, it was seen that at a given time, the creep strains were much lower for the aged samples relative to the non-aged samples. Thermal aging has a significant effect on the secondary creep rate, which decreases with both the aging temperature and the aging time. Up to a 100X reduction in the creep rate was observed, and the major changes occurred during the first 50 days of the isothermal aging.


2017 ◽  
Vol 137 (6) ◽  
pp. 152-158
Author(s):  
Satoshi Inoue ◽  
Takuya Takahashi ◽  
Momoko Kumemura ◽  
Kazunori Ishibashi ◽  
Hiroyuki Fujita ◽  
...  

Author(s):  
X. Long ◽  
I. Dutta ◽  
R. Guduru ◽  
R. Prasanna ◽  
M. Pacheco

A thermo-mechanical loading system, which can superimpose a temperature and location dependent strain on solder joints, is proposed in order to conduct highly accelerated thermal-mechanical cycling (HATC) tests to assess thermal fatigue reliability of Ball Grid Array (BGA) solder joints in microelectronics packages. The application of this temperature and position dependent strain produces generally similar loading modes (shear and tension) encountered by BGA solder joints during service, but substantially enhances the inelastic strain accumulated during thermal cycling over the same temperature range as conventional ATC (accelerated thermal cycling) tests, thereby leading to a substantial acceleration of low-cycle fatigue damage. Finite element analysis was conducted to aid the design of experimental apparatus and to predict the fatigue life of solder joints in HATC testing. Detailed analysis of the loading locations required to produce failure at the appropriate joint (next to the die-edge ball) under the appropriate tension/shear stress partition are presented. The simulations showed that the proposed HATC test constitutes a valid methodology for further accelerating conventional ATC tests. An experimental apparatus, capable of applying the requisite loads to a BGA package was constructed, and experiments were conducted under both HATC and ATC conditions. It is shown that HATC proffers much reduced cycling times compared to ATC.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001253-001283
Author(s):  
Satoshi Okude ◽  
Kazushisa Itoi ◽  
Masahiro Okamoto ◽  
Nobuki Ueta ◽  
Osamu Nakao

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.


Author(s):  
Phani Vallabhajosyula

Mixed technology applications for Flip-Chip (FC) / SMT require special step stencil designs where flux is printed first for the FC and SMD paste printed next with a second stencil that has a relief pocket etched or formed in the FC area. Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, Step Stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. However as SMT requirements became more complex and consequently more demanding so did the requirements for complex Step Stencils. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 40um with steps of 13um are used to obtain desired print volume. These applications and the associated stencil design to achieve a solution will be discussed in detail in this paper. Various print experiments will be conducted and print quality will be determined by visual inspection and 3D measurement of the paste deposit to understand the volume transfer efficiency.


2005 ◽  
Vol 2 (4) ◽  
pp. 269-280 ◽  
Author(s):  
Lafir Ali ◽  
Y. C. Chan ◽  
M.O. Alam

The reliability of ACF (Anisotropic conductive film) interconnection is a serious concern especially under thermal loading condition. This paper focuses on the online contact resistance behavior of the ACF joint for bumpless flip-chip on flex packages during different thermal cycling conditions. In this work, flip chips of 11×3 mm2 having bare aluminum pad were used. Real time contact resistance (i.e. live measurement contact resistance variation with temperature) was measured by four points probe method when the packages were inside thermal shock chamber. Tests for three different thermal cycling profiles (125°C to −55°C, 140°C to −40°C and 150°C to −65°C) were carried out. The samples bonded at temperature 180°C and pressure of 2.42Mpa was used. The initial contact resistance of the bumpless samples was 0.4Ω. Contact resistance increased with the number of thermal cycles, however the effect was severe when the temperature variation was above the glass transition temperature (Tg) of the ACF matrix (131°C). Differences in co-efficient of thermal expansion (CTE) between the chip and the substrate generated thermal stresses during temperature fluctuation, which caused the pad of the substrate to slide over the Al pad of the chip. Thus variation of the contact resistance was also observed along the interconnection position in the package, i.e. corner joint showed higher value of increase in contact resistance than the middle position. Even though flex substrate was used in this study; the sliding effect was severe at the corner Al pads of the chip, where cumulative forces generated due to the thermal stress. Results show that for thermal cycling profile 140°C to −40°C, online contact resistance increased to 1.2 Ω in corner joint, whereas for the middle joints the contact resistance just increased to 0.5 Ω. Glass transition temperature (Tg) of the ACF material plays an important role on the high temperature contact resistance. For every thermal cycling profile, there is an incubation period that would have significant impact in the application of ACF. After the incubation period the contact resistance increases rapidly and the joints are no longer reliable.


1998 ◽  
Vol 120 (4) ◽  
pp. 322-327 ◽  
Author(s):  
H. Doi ◽  
K. Kawano ◽  
A. Yasukawa ◽  
T. Sato

The effect of a heat spreader on the life of the solder joints for underfill-encapsulated, flip-chip packages is investigated through stress analyses and thermal cycling tests. An underfill with suitable mechanical properties is found to be able to prolong the fatigue life of the solder joints even in a package with a heat spreader and an alumina substrate. The delamination of the underfill from the chip is revealed as another critical failure mode for which the shape of the underfill fillet has a large effect.


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