Reliability of Underfill-Encapsulated Flip-Chips With Heat Spreaders

1998 ◽  
Vol 120 (4) ◽  
pp. 322-327 ◽  
Author(s):  
H. Doi ◽  
K. Kawano ◽  
A. Yasukawa ◽  
T. Sato

The effect of a heat spreader on the life of the solder joints for underfill-encapsulated, flip-chip packages is investigated through stress analyses and thermal cycling tests. An underfill with suitable mechanical properties is found to be able to prolong the fatigue life of the solder joints even in a package with a heat spreader and an alumina substrate. The delamination of the underfill from the chip is revealed as another critical failure mode for which the shape of the underfill fillet has a large effect.

2020 ◽  
Author(s):  
Hui YANG ◽  
Jihui Wu

Abstract The simulation of nano-silver solder joints in flip-chips is performed by the finite element software ANSYS, and the stress-strain distribution results of the solder joints are displayed. In this simulation, the solder joints use Anand viscoplastic constitutive model, which can reasonably simulate the stress and strain of solder joints under thermal cycling load. At the same time this model has been embedded in ANSYS software, so it is more convenient to use. The final simulation results show that the areas where the maximum stresses and strains occur at the solder joints are mostly distributed in the contact areas between the solder joints and the copper pillars and at the solder joints. During the entire thermal cycling load process, the area where the maximum change in stress and strain occurs is always at the solder joint, and when the temperature changes, the temperature at the solder joint changes significantly. Based on comprehensive analysis, the relevant empirical correction calculation equation is used to calculate and predict the thermal fatigue life of nano-silver solder joints. The analysis results provide a reference for the application of nano-silver solder in the electronic packaging industry.


2020 ◽  
Author(s):  
Hui Yang ◽  
Jihui Wu

Abstract The simulation of nano-silver solder joints in flip-chips is performed by the finite element software ANSYS, and the stress-strain distribution results of the solder joints are displayed. In this simulation, the solder joints use Anand viscoplastic constitutive model, which can reasonably simulate the stress and strain of solder joints under thermal cycling load. At the same time this model has been embedded in ANSYS software, so it is more convenient to use. The final simulation results show that the areas where the maximum stresses and strains occur at the solder joints are mostly distributed in the contact areas between the solder joints and the copper pillars and at the solder joints. During the entire thermal cycling load process, the area where the maximum change in stress and strain occurs is always at the solder joint, and when the temperature changes, the temperature at the solder joint changes significantly. Based on comprehensive analysis, the relevant empirical correction calculation equation is used to calculate and predict the thermal fatigue life of nano-silver solder joints. The analysis results provide a reference for the application of nano-silver solder in the electronic packaging industry.


1999 ◽  
Vol 121 (2) ◽  
pp. 61-68 ◽  
Author(s):  
R. Chandaroy ◽  
C. Basaran

In the electronic industry, the dominant failure mode for solder joints is assumed to be thermal cycling. When semiconductor devices are used in vibrating environment, such as automotive and military applications, dynamic stresses contribute to the failure mechanism of the solder joint, and can become the dominant failure mode. In this paper, a damage mechanics based unified constitutive model for Pb40/Sn60 solder joints has been developed to accurately predict the thermomechanical behavior of solder joints under concurrent thermal and dynamic loading. It is shown that simultaneous application of thermal and dynamic loads significantly shorten the fatigue life. Hence, damage induced in the solder joint by the vibrations have to be included, in fatigue life predictions to correctly predict the reliability of solder joints. The common practice of relating only thermal cycling induced inelastic strain to fatigue life can be inadequate to predict solder joint reliability. A series of parametric studies were conducted to show that contrary to popular opinion all dynamic loading induced strains are not elastic. Hence, vibrations can significantly affect the fatigue life and reliability of solder joints in spite of their small mass.


2020 ◽  
Author(s):  
Hui Yang ◽  
Jihui Wu

Abstract The simulation of nano-silver solder joints in flip-chips is performed by the finite element software ANSYS, and the stress-strain distribution results of the solder joints are displayed. In this simulation, the solder joints use Anand viscoplastic constitutive model, which can reasonably simulate the stress and strain of solder joints under thermal cycling load. At the same time this model has been embedded in ANSYS software, so it is more convenient to use. The final simulation results show that the areas where the maximum stresses and strains occur at the solder joints are mostly distributed in the contact areas between the solder joints and the copper pillars and at the solder joints. During the entire thermal cycling load process, the area where the maximum change in stress and strain occurs is always at the solder joint, and when the temperature changes, the temperature at the solder joint changes significantly. Based on comprehensive analysis, the relevant empirical correction calculation equation is used to calculate and predict the thermal fatigue life of nano-silver solder joints. The analysis results provide a reference for the application of nano-silver solder in the electronic packaging industry.


1994 ◽  
Vol 116 (3) ◽  
pp. 163-170 ◽  
Author(s):  
Tsung-Yu Pan

In the automotive and computer industries, a perennial challenge has been to design an adequate and efficient accelerated thermal cycling test which would correspond to field service conditions. Failures, induced in both thermal cycle testing and field service, are characterized by thermal fatigue behavior. Several fatigue models have been proposed, none of these models take into account all of the many parameters of the test or service environment. In thermal cycling, for example, the temperature range, ramp rate, hold time, and stepped heating and cooling are known to influence the number of cycles to failure. In this study, a critical accumulated strain energy (CASE) failure criterion is proposed to correlate the fatigue life to both the plastic and creep strain energies, which accumulate in solder joints during the thermal cycling. This criterion suggests that solder joints fail as the strain energy accumulates and reaches a critical value. By using finite element analysis with a “ladder” procedure, both time-independent plastic strain energy and time-dependent creep strain energy are quantified. These are related to fatigue life by the equation: C = N*f (Ep + 0.13Ec), where C is the critical strain energy density, Nf is the fatigue life, Ep and Ec are plastic and creep strain energy density accumulation per cycle, respectively, for the eutectic Sn-Pb solders. By analyzing Hall and Sherry’s thermal cycling data (Hall and Sherry, 1986), it is found that creep is the predominant factor in deciding fatigue life. Creep accounts for 51 to 97 percent of the total accumulated strain energy, depending on the cycling profiles. This criterion is used to simulate crack propagation in a solder joint by analyzing the strain energy in small “domains” within the joint.


2013 ◽  
Vol 53 (5) ◽  
pp. 741-747 ◽  
Author(s):  
Shoho Ishikawa ◽  
Hironori Tohmyoh ◽  
Satoshi Watanabe ◽  
Tomonori Nishimura ◽  
Yoshikatsu Nakano

2015 ◽  
Vol 27 (4) ◽  
pp. 178-184 ◽  
Author(s):  
Ye Tian ◽  
Justin Chow ◽  
Xi Liu ◽  
Suresh K. Sitaraman

Purpose – The purpose of this paper is to study the intermetallic compound (IMC) thickness, composition and morphology in 100-μm pitch and 200-μm pitch Sn–Ag–Cu (SAC305) flip-chip assemblies after bump reflow and assembly reflow. In particular, emphasis is placed on the effect of solder joint size on the interfacial IMCs between metal pads and solder matrix. Design/methodology/approach – This work uses 100-μm pitch and 200-μm pitch silicon flip chips with nickel (Ni) pads and stand-off height of approximately 45 and 90 μm, respectively, assembled on substrates with copper (Cu) pads. The IMCs evolution in solder joints was investigated during reflow by using 100- and 200-μm pitch flip-chip assemblies. Findings – After bump reflow, the joints size controls the IMC composition and dominant IMC type as well as IMC thickness and also influences the dominant IMC morphology. After assembly reflow, the cross-reaction of the pad metallurgies promotes the dominant IMC transformation and shape coarsened on the Ni pad interface for smaller joints and promotes a great number of new dominate IMC growth on the Ni pad interface in larger joints. On the Cu pad interface, many small voids formed in the IMC in larger joints, but were not observed in smaller joints, combined with the drawing of the IMC growth process. Originality/value – With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 to150 μm. This work shows that as the packaging size reduced with the solder joint interconnection, the solder size becomes an important factor in the intermetallic composition as well as morphology and thickness after reflow.


2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.


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