Die Stress Variation During Thermal Cycling Reliability Tests

2007 ◽  
Author(s):  
M. Kaysar Rahim ◽  
Jordan Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Thermal Cycling ◽  
Electronic Packaging ◽  
Room Temperature ◽  
Flip Chip ◽  
Constitutive Relations ◽  
Temperature Cycling ◽  
Material Behavior ◽  
Aging Effects ◽  
Test Chips

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete three-dimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 × 5 mm perimeter bumped die were assembled on FR-406 substrates. Three different thermal cycling temperature profiles were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.

Stresses in Area Array Assemblies Subjected to Thermal Cycling

2009 ◽  
Author(s):  
Jordan Roberts ◽  
M. Kaysar Rahim ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Temperature Cycling ◽  
Aging Effects ◽  
Area Array ◽  
Die Surface ◽  
Test Chips

Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, −40 to 125 °C, and −55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

Characterization of Die Stress Distributions in Area Array Flip Chip Packaging

2009 ◽  
Author(s):  
Jordan Roberts ◽  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Power ◽  
Temperature Cycling ◽  
Aging Effects ◽  
Area Array ◽  
Power Cycling ◽  
Die Stress ◽  
On Chip ◽  
Test Chips

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during thermal cycling and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach also allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, initial experiments have been performed to analyze the effects of thermal cycling and power cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). Power cycling of selected parts was performed by exciting the on-chip heaters on the test chips with power levels typical of microprocessor die. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show some cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of temperature cycling duration are currently being correlated with the delaminations occurring at the interfaces between the die and underfill and the die and lid adhesive. In addition, finite element models of the packages are being developed and correlated with the data.

Aging Effects on the Mechanical Behavior and Reliability of SAC Alloys

2009 ◽  
Author(s):  
Yifei Zhang ◽  
Zijie Cai ◽  
Jeffrey C. Suhling ◽  
Pradeep Lall
Keyword(s):  
Thermal Cycling ◽  
Mechanical Behavior ◽  
Room Temperature ◽  
Material Behavior ◽  
Lead Free ◽  
Lead Free Solder ◽  
Aging Effects ◽  
Free Solder ◽  
Effects Of Aging ◽  
Temperature Aging

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that the observed material behavior variations of Sn-Ag-Cu (SAC) lead free solders during room temperature aging (25°C) and elevated temperature aging (125°C) were unexpectedly large and universally detrimental to reliability. Such effects for lead free solder materials are especially important for the harsh applications environments present in high performance computing and in automotive, aerospace, and defense applications. However, there has been little work in the literature, and the work that has been done has concentrated on the degradation of solder ball shear strength (e.g. Dage Shear Tester). Current finite element models for solder joint reliability during thermal cycling accelerated life testing are based on traditional solder constitutive and failure models that do not evolve with material aging. Thus, there will be significant errors in the calculations with the new lead free SAC alloys that illustrate dramatic aging phenomena. In the current work, we have extended our previous studies to include a full test matrix of aging temperatures and solder alloys. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on four different SAC alloys (SAC105, SAC205, SAC305, SAC405) that were aged for various durations (0–6 months) at room temperature (25°C), and several elevated temperatures (50, 75, 100, and 125°C). Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. Variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and aging temperature. In this paper, we report on the creep results. The chosen selection of SAC alloys has allowed us to explore the effects of silver content on aging behavior (we have examined SACN05 with N = 1%, 2%, 3%, and 4% silver; with all alloys containing 0.5% copper). In order to reduce the aging induced degradation of the material behavior of the SAC alloys, we are testing several doped SAC alloys in our ongoing work. These materials include SAC0307-X, SAC105-X, and SAC305-X; where the standard SAC alloys have been modified by the addition of small percentages of one or more additional elements (X). Using dopants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, etc.) has become widespread to enhance shock/drop reliability, and we have extended this approach to examine the ability of dopants to reduce the effects of aging and extend thermal cycling reliability.

Evolution of the Stress-Strain and Creep Behavior of Underfill Encapsulants With Aging

2009 ◽  
Author(s):  
Chang Lin ◽  
Jeffrey C. Suhling ◽  
Pradeep Lall
Keyword(s):  
Creep Rate ◽  
Thermal Cycling ◽  
Aging Time ◽  
Aging Temperature ◽  
Isothermal Aging ◽  
Flip Chip ◽  
Material Behavior ◽  
Initial Slope ◽  
Aging Effects ◽  
Stress Strain

Microelectronic encapsulants exhibit evolving properties that change significantly with environmental exposures such as isothermal aging and thermal cycling. Such aging effects are exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In this work, measurements of material behavior changes occurring in flip chip underfill encapsulants exposed to isothermal aging have been performed. A novel method has been developed to fabricate freestanding underfill uniaxial test specimens so that they accurately reflect the encapsulant layer present in flip chip assemblies. Using the developed specimen preparation procedure, isothermal aging effects have been characterized at several elevated temperatures (+ 80, +100, + 125, and +150 °C). Samples have been aged at the four temperatures for periods up to 6 months. Stress-strain and creep tests have been performed on non-aged and aged samples, and the changes in mechanical behavior have been recorded for the various aging temperatures and durations of isothermal exposure. Empirical models have been developed to predict the evolution of the material properties (modulus, strength) and the creep strain rate as a function of temperature, aging time, and aging temperature. The evaluated underfill illustrated softening behavior at temperatures exceeding 100 °C, although the documented Tg ranged from 130–150 °C. The obtained results showed an obvious enhancement of the underfill mechanical properties as a function of the aging temperature and aging time. Both the effective elastic modulus (initial slope) and ultimate tensile strength (highest stress before failure) increase monotonically with the amount of isothermal aging or aging temperature, regardless of whether the aging temperature is below, at, or above the Tg of the material. From the creep results, it was seen that at a given time, the creep strains were much lower for the aged samples relative to the non-aged samples. Thermal aging has a significant effect on the secondary creep rate, which decreases with both the aging temperature and the aging time. Up to a 100X reduction in the creep rate was observed, and the major changes occurred during the first 50 days of the isothermal aging.

Measurement of Microprocessor Die Stress due to Thermal Cycling, Power Cycling, and Second Level Assembly

2013 ◽  
Author(s):  
Jordan C. Roberts ◽  
Mohammad Motalab ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Power ◽  
Three Dimensional ◽  
Power Cycling ◽  
Die Stress ◽  
Test Chips ◽  
Resistance Data ◽  
Critical Locations

In the current work, we have extended our past studies on Flip Chip Ceramic Ball Grid Array (FC-BGA) microprocessor packaging configurations to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings. Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time.

High Reliability Flip Chip Using Low CTE Laminate Substrates

2005 ◽  
Author(s):  
D. Scott Copeland ◽  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
Guoyun Tian ◽  
Pradeep Lall ◽  
...  
Keyword(s):  
Carbon Fiber ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Experimental Testing ◽  
High Reliability ◽  
Low Cost ◽  
Substrate Material ◽  
Space Applications ◽  
Sandwich Construction ◽  
Test Chips

In this work, we report on our efforts to develop high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. −55 to 150 °C). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR®). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and un-pressurized space applications.

Mechanical Reliability and Bump Degradation of ACF Flip Chip Packages Using BCB (Cyclotene™) Bumping Dielectrics Under Temperature Cycling

2004 ◽  
Vol 126 (2) ◽  
pp. 202-207 ◽  
Author(s):  
Woon-Seong Kwon ◽  
Hyoung-Joon Kim ◽  
Kyung-Wook Paik ◽  
Se-Young Jang ◽  
Soon-Min Hong
Keyword(s):  
Fracture Surface ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Dissimilar Materials ◽  
Damage Mechanism ◽  
Temperature Cycling ◽  
Mechanical Reliability ◽  
Cyclic Shear ◽  
Electrical Failure ◽  
Anisotropic Conductive Adhesive

Interface degradation between dissimilar materials in the flip chip packages with anisotropic conductive adhesive joint is susceptible to mechanical and electrical failure upon temperature cycling. Particularly the mechanical reliability of flip chip using anisotropic conductive films (ACFs) often depends upon the interface characteristics between the bumping/passivation dielectrics and adjacent materials. This paper investigates the delamination and cracking in polymeric bumping/passivation dielectrics (Cyclotene™ 4024) and the damage mechanism of interconnect bump with BCB bumping dielectrics upon temperature cycling. Adhesion and fracture surface morphology after die shear testing show that the weakening and delamination of BCB passivation layer at the die corner is the main cause of the reduction of die adhesion strength after the thermal cycling. The sliding trace on fracture surface after three-point bending fracture reveals that cyclic shear displacement in a polymeric BCB layer fatigue the interface bonding or interconnect bump upon thermal cycling, leading to mechanical delamination and functional bump failure. Passivation cracks also develop around the circumference of BCB passivation over aluminum pad. A model is presented for the degradation of interconnect bump with surrounding BCB passivation.

Shape training of Ge precipitates in an Al-1.8at% Ge alloy

1994 ◽  
Vol 52 ◽  
pp. 690-691
Author(s):  
S. Hinderberger ◽  
S. Q. Xiao ◽  
K. H. Westmacott ◽  
U. Dahmen
Keyword(s):  
Room Temperature ◽  
Equilibrium Shape ◽  
Bulk Sample ◽  
Temperature Cycling ◽  
Orientation Relationships ◽  
Rich Variety ◽  
Direct Observations ◽  
Equilibrium Shapes ◽  
Ice Water

Ge precipitates in Al are known to form in a rich variety of shapes and orientation relationships. In this work it is shown that initial non-equilibrium shapes such as plates, laths, needles and tetrahedra can be induced to change to the equilibrium shape of an octahedron by proper temperature cycling. Analysis of this effect in bulk samples was complemented by direct observations of its mechanisms during in-situ temperature cycling.A bulk sample of an Al-1.8at%Ge alloy was solid solution annealed at 420°C for 2h, quenched in ice water, pre-aged at room temperature for 72h and then annealed for 5h at 250°C. Subsequently, part of the sample was repeatedly cycled between 250°C and 360°C. TEM specimens were prepared from both the cycled and non-cycled bulk sample by conventional electropolishing and examined in a JEOL 200CX electron microscope. The in-situ temperature cycling was carried out in a Kratos 1.5 MeV HVEM equipped with a double tilt heating stage.

Thermal Cycling Guidelines for Automotive, Computer, Portable, and Implantable Medical Device Applications

2000 ◽  
Author(s):  
Rajiv Raghunathan ◽  
Raghuram V. Pucha ◽  
Suresh K. Sitaraman
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Inelastic Strain ◽  
Computer Applications ◽  
Material Behavior ◽  
Implantable Medical Device ◽  
Implantable Medical Devices ◽  
Device Applications ◽  
Component Assembly ◽  
Virtual Qualification

Abstract The objective of this work is to develop qualification guidelines for Flip-Chip on Board (FCOB) and Flip Chip Chip-Scale Packages (FCCSP) used in implantable medical devices, automotive applications, computer applications and portables, taking into consideration the thermal history associated with the field conditions. The accumulated equivalent inelastic strain per cycle and the maximum strain energy density have been used as damage parameters to correlate solder fatigue damage during field use and thermal cycling. The component assembly process mechanics, the time and temperature-dependent material behavior, and the critical geometric features of the assembly have been taken into consideration for developing the comprehensive virtual qualification methodology.

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