Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

2019 ◽  
Vol 141 (4) ◽  
Author(s):  
John H. Lau
Keyword(s):  
Thermal Cycling ◽  
Thermal Performance ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Direct Imaging ◽  
Printed Circuit ◽  
Thermal Cycling Condition ◽  
Recent Advances ◽  
Cycling Condition

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

Thermal Performance of Microelectronic Substrates With Submillimeter Integrated Vapor Chamber

2019 ◽  
Vol 141 (5) ◽  
Author(s):  
Sangbeom Cho ◽  
Yogendra Joshi
Keyword(s):  
Heat Transfer ◽  
Thermal Performance ◽  
Printed Circuit Board ◽  
Mechanical Design ◽  
Three Dimensional ◽  
Circuit Board ◽  
Working Fluid ◽  
Vapor Chamber ◽  
Conduction Model ◽  
Printed Circuit

We develop a vapor chamber integrated with a microelectronic packaging substrate and characterize its heat transfer performance. A prototype of vapor chamber integrated printed circuit board (PCB) is fabricated through successful completion of the following tasks: patterning copper micropillar wick structures on PCB, mechanical design and fabrication of condenser, device sealing, and device vacuuming and charging with working fluid. Two prototype vapor chambers with distinct micropillar array designs are fabricated, and their thermal performance tested under various heat inputs supplied from a 2 mm × 2 mm heat source. Thermal performance of the device improves with heat inputs, with the maximum performance of ∼20% over copper plated PCB with the same thickness. A three-dimensional computational fluid dynamics/heat transfer (CFD/HT) numerical model of the vapor chamber, coupled with the conduction model of the packaging substrate is developed, and the results are compared with test data.

Causes of Degradation of Thermal Performance of Ball Grid Arrays After Thermal Cycling

2007 ◽  
Author(s):  
Roy W. Knight ◽  
Yasser Elkady ◽  
Jeffrey C. Suhling ◽  
Pradeep Lall
Keyword(s):  
Solder Joint ◽  
Thermal Resistance ◽  
Thermal Cycling ◽  
Thermal Performance ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Element Analysis ◽  
Solder Balls ◽  
Ball Grid Array Packages ◽  
The Impact

The thermal performance of Ball Grid Array packages depends upon many parameters including die size, use of thermal balls, number of perimeter balls, use of underfill, and printed circuit board heat spreader and thermal via design. Thermal cycling can affect the integrity of thermal paths in and around the BGA as a result of the cracking of solder balls and delamination of the package, including at underfill interfaces. In this study, the impact of thermal cycling on the thermal performance of BGA’s was investigated and quantified. A number of test boards which included a range of the parameters cited above were experimentally examined. A baseline thermal resistance was measured for each case, which was verified with numerical thermal modeling. The boards were then subjected to thermal cycling from −40°C to 125°C. Every 250 cycles the thermal performance was measured. Packages expected to be least reliable (with large die and no underfill), showed an increase in thermal resistance after 750 thermal cycles. Further increases in thermal resistance were observed with continuous thermal cycling until solder joint failure occurred at 1250 cycles, preventing additional measurements. Finite element analysis identified critical thermal and perimeter solder balls as the most likely sites for cracking. Boards were cross-sectioned and examined for solder joint cracks and delamination to identify the cause for the observed increases in thermal resistance. Cracking was found in the critical thermal and perimeter solder balls.

The Effects of Variations in Manufacturing on PCB Thermal Properties

2011 ◽  
Author(s):  
John F. Maddox ◽  
Roy W. Knight ◽  
Sushil H. Bhavnani
Keyword(s):  
Thermal Properties ◽  
Steady State ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Manufacturing Process ◽  
Printed Circuit Board ◽  
Electronic Device ◽  
Circuit Board ◽  
Printed Circuit

The thermal performance of an electronic device is heavily dependent on the properties of the printed circuit board (PCB) to which it is attached. However, even small variations in the process used to fabricate a PCB can have drastic effects on its thermal properties. Therefore, it is necessary to experimentally verify that each stage in the manufacturing process is producing the desired result. Steady state thermal resistance measurements, taken with a comparative cut bar apparatus based on ASTM D 5470-06, were used to compare PCBs manufactured from the same design by different vendors and the effects of vias filled with epoxy versus unfilled vias on the thermal resistance of a PCB. It was found that the thermal resistance of the PCBs varied by as much as 30% between vendors and that the PCBs with epoxy filled vias had a higher thermal resistance than those with unfilled vias, possibly due to the order in which the manufacturing steps were taken.

An Assessment of the Impact of Interconnect Strategies on Thermal Performance of GaAs Power Amplifier IC Devices

2001 ◽  
Author(s):  
V. H. Adams ◽  
T.-Y. Tom Lee
Keyword(s):  
Thermal Resistance ◽  
Power Amplifier ◽  
Thermal Performance ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Wire Bond ◽  
Die Attach ◽  
The Impact

Abstract Alternative interconnect strategies are being considered in place of the standard wire bond interconnect for GaAs power amplifier MMIC devices due to cost and electrical performance improvements. The package/die thermal performance consequences are potentially high-risk issue to these interconnect strategies and requires evaluation. Thermal simulations are conducted to compare and evaluate the thermal performances of three interconnect strategies: wire bond, gold post-flip chip, and through via interconnects. The test vehicle simulated is a three-stage, dual band power amplifier integrated circuit dissipating approximately 5 W steady-state power. Parametric studies are conducted to evaluate the impact of the printed circuit board, die thickness, solid gold vias, and design enhancements on package thermal performance. Best thermal performance is provided by a wire bonded, thin GaAs die attached with solder die attach to a printed circuit board that maximizes the number of plated-through-holes directly under the die. This configuration results in a best case junction-to-heat sink thermal resistance of 12 °C/W. Optimum flip chip and through via designs result in degraded thermal performance compared to the above described wire bond design but may have acceptable thermal performance. For these simulations, predicted junction-to-heatsink thermal resistance is in a range of 15–20 °C/W and is better than a comparable wire bonded design that uses a conductive epoxy die attach material.

scholarly journals Surface Mounting of Leadless Chip Carriers on Various Printed Circuit Board Type Substrates

1982 ◽  
Vol 10 (1) ◽  
pp. 13-21 ◽  
Author(s):  
I. G. Lang
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Test Results ◽  
Printed Circuit ◽  
Board Type ◽  
Surface Mounting

The effect of extended thermal cycling on the reliability of joints between ceramic leadless chip carriers and various printed circuit board type substrates is examined. Test results indicate success in using ceramic leadless chip carriers on some styles of PCB.

Reliability of Flex Coatings for High-Performance Applications

1993 ◽  
Vol 323 ◽  
Author(s):  
H. Tong ◽  
C. Wilson ◽  
T. Graham ◽  
L. Shi
Keyword(s):  
Thin Film ◽  
Thermal Cycling ◽  
High Performance ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Polymeric Coatings ◽  
Printed Circuit ◽  
Thin Film Silicon ◽  
Edge Connector

AbstractA study was undertaken to select a suitable coating for a high-pin-count flexible edge connector (Flex) that interconnected a multichip thin-film silicon carrier to a printed circuit board. The Flex with cantilevered inner leads were joined to the contact pads at the perimeter of the carrier. 15 polymeric coatings were evaluated by subjecting coated Flexes to tests consisting of inner lead bending, temperature/humidity/bias (85°C/80%/15 V/350 hours), corrosion, line peel, and/or pressure cooker (126°C/20 psig/120 hours). Inner lead bending measurements were performed to assess the potential of lead shorting at the inner lead bonding sites during thermal cycling. From this study, a low-stress silicone evolved as the best candidate. The results leading to this conclusion will be shown and discussed.

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