Sequential combined thermal cycling and vibration test and simulation of printed circuit board

2018 ◽  
Vol 88-90 ◽  
pp. 768-773 ◽  
Author(s):  
F. Arabi ◽  
A. Gracia ◽  
J.-Y. Delétage ◽  
H. Frémont
2019 ◽  
Vol 141 (4) ◽  
Author(s):  
John H. Lau

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.


1982 ◽  
Vol 10 (1) ◽  
pp. 13-21 ◽  
Author(s):  
I. G. Lang

The effect of extended thermal cycling on the reliability of joints between ceramic leadless chip carriers and various printed circuit board type substrates is examined. Test results indicate success in using ceramic leadless chip carriers on some styles of PCB.


1993 ◽  
Vol 323 ◽  
Author(s):  
H. Tong ◽  
C. Wilson ◽  
T. Graham ◽  
L. Shi

AbstractA study was undertaken to select a suitable coating for a high-pin-count flexible edge connector (Flex) that interconnected a multichip thin-film silicon carrier to a printed circuit board. The Flex with cantilevered inner leads were joined to the contact pads at the perimeter of the carrier. 15 polymeric coatings were evaluated by subjecting coated Flexes to tests consisting of inner lead bending, temperature/humidity/bias (85°C/80%/15 V/350 hours), corrosion, line peel, and/or pressure cooker (126°C/20 psig/120 hours). Inner lead bending measurements were performed to assess the potential of lead shorting at the inner lead bonding sites during thermal cycling. From this study, a low-stress silicone evolved as the best candidate. The results leading to this conclusion will be shown and discussed.


2012 ◽  
Vol 132 (6) ◽  
pp. 404-410 ◽  
Author(s):  
Kenichi Nakayama ◽  
Kenichi Kagoshima ◽  
Shigeki Takeda

2014 ◽  
Vol 5 (1) ◽  
pp. 737-741
Author(s):  
Alejandro Dueñas Jiménez ◽  
Francisco Jiménez Hernández

Because of the high volume of processing, transmission, and information storage, electronic systems presently requires faster clock speeds tosynchronizethe integrated circuits. Presently the “speeds” on the connections of a printed circuit board (PCB) are in the order of the GHz. At these frequencies the behavior of the interconnects are more like that of a transmission line, and hence distortion, delay, and phase shift- effects caused by phenomena like cross talk, ringing and over shot are present and may be undesirable for the performance of a circuit or system.Some of these phrases were extracted from the chapter eight of book “2-D Electromagnetic Simulation of Passive Microstrip Circuits” from the corresponding author of this paper.


Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.


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