Elastic Analysis of Flip-Chip Solder Joints Undergoing Thermal Excursions

1994 ◽  
Vol 116 (2) ◽  
pp. 110-115 ◽  
Author(s):  
H. D. Conway ◽  
P. Bo̸rgesen ◽  
C.-Y. Li
Keyword(s):  
Elastic Deformation ◽  
Quantitative Evaluation ◽  
Flip Chip ◽  
Solder Joints ◽  
Elastic Analysis ◽  
Power Cycles ◽  
Qualitative Understanding ◽  
Area Array

An elastic analysis is developed to provide estimates of the stresses in area array solder joints during thermal excursions. The analysis provides a rapid quantitative evaluation of the important stresses during elastic deformation, and may serve as a basis for the qualitative understanding of the loading of interconnects during thermal and power cycles.

Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies

2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mirror Image ◽  
Circuit Board ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Area Array ◽  
Plastic Ball

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.

Predicting Technique of Delamination at Adhesively Bonding Joints in a Flip Chip Package During Solder Reflow Process

2005 ◽  
Author(s):  
Toru Ikeda ◽  
Won-Keun Kim ◽  
Noriyuki Miyazaki
Keyword(s):  
Stress Intensity ◽  
Vapor Pressure ◽  
Quantitative Evaluation ◽  
Flip Chip ◽  
Moisture Absorption ◽  
Solder Joints ◽  
Reflow Process ◽  
Sensitivity Tests ◽  
Solder Reflow ◽  
Chip Size

Recently, adhesively bonding techniques such as the anisotropic conductive film (ACF) or the non-conductive adhesive resin are often used for connections in the chip size packages instead of conventional solder joints due to their reasonable cost and the ease of miniaturization. Adhesively bonding techniques expected to be a key technology for the chip size packaging and the system in package. However, the level of reliability for adhesively bonding techniques is still less than that for solder joints. The quantitative evaluation techniques for the reliability of adhesively bonding techniques are desired. This paper focused on the reliability of adhesively bonding joints in a flip chip package during the solder reflow process for other solder jointed devices. This paper presents a methodology for quantitative evaluation of the delamination in a flip chip interconnected by an ACF under moisture/reflow sensitivity tests. The delamination toughnesses between components in a flip chip based on the stress intensity factors were measured by fracture tests in conjunction with the numerical analysis developed in our previous study. Moisture concentration after moisture absorption was expected by the diffusion analysis using the finite element method. Then, vapor pressure in a flip chip during the solder reflow process was estimated. Finally the delamination was predicted by comparing the stress intensity factor of an interface crack due to vapor pressure with the delamination toughness. The delaminations in an actual flip chip package during moisture/reflow sensitivity tests have successfully predicted by the present methodology.

Rapid diagnosis of electromigration induced failure time of Pb-free flip chip solder joints by high resolution synchrotron radiation laminography

2011 ◽  
Vol 99 (8) ◽  
pp. 082114 ◽  
Author(s):  
Tian Tian ◽  
Feng Xu ◽  
Jung Kyu Han ◽  
Daechul Choi ◽  
Yin Cheng ◽  
...  
Keyword(s):  
High Resolution ◽  
Synchrotron Radiation ◽  
Flip Chip ◽  
Solder Joints ◽  
Failure Time ◽  
Rapid Diagnosis

Crack Propagation Experiments on Flip Chip Solder Joints

1998 ◽  
Vol 515 ◽  
Author(s):  
S. Wiese ◽  
F. Feustel ◽  
S. Rzepka ◽  
E. Meusel
Keyword(s):  
Crack Propagation ◽  
Flip Chip ◽  
Solder Joints ◽  
Shear Loading ◽  
Displacement Curve ◽  
In Situ Experiments ◽  
Propagation Experiment ◽  
Crack Propagation Experiment ◽  
Number Of Cycles ◽  
Force Displacement

ABSTRACTThe paper presents crack propagation experiments on real flip chip specimens applied to reversible shear loading. Two specially designed micro testers will be introduced. The first tester provides very precise measurements of the force displacement hysteresis. The achieved resolutions have been I mN for force and 20 nm for displacement. The second micro tester works similar to the first one, but is designed for in-situ experiments inside the SEM. Since it needs to be very small in size it reaches only resolutions of 10 mN and 100nm, which is sufficient to achieve equivalence to the first tester. A cyclic triangular strain wave is used as load profile for the crack propagation experiment. The experiment was done with both machines applying equivalent specimens and load. The force displacement curve was recorded using the first micro mechanical tester. From those hysteresis, the force amplitude has been determined for every cycle. All force amplitudes are plotted versus the number of cycles in order to quantify the crack length. With the second tester, images were taken at every 10th … 100th cycle in order to locate the crack propagation. Finally both results have been linked together for a combined quatitive and spatial description of the crack propagation in flip chip solder joints.

Effect of entropy production on microstructure change in eutectic SnPb flip chip solder joints by thermomigration

2006 ◽  
Vol 89 (22) ◽  
pp. 221906 ◽  
Author(s):  
Fan-Yi Ouyang ◽  
K. N. Tu ◽  
Yi-Shao Lai ◽  
Andriy M. Gusak
Keyword(s):  
Entropy Production ◽  
Flip Chip ◽  
Solder Joints ◽  
Microstructure Change ◽  
Eutectic Snpb

Area Array Solder Joints for Passive Alignment

1992 ◽  
Vol 264 ◽  
Author(s):  
John McGroarty ◽  
Boris Yost ◽  
Peter Børgesen ◽  
Che-Yu Li
Keyword(s):  
Optical Interconnects ◽  
Solder Joints ◽  
Cost Effective ◽  
Scientific Basis ◽  
Electronic Packages ◽  
Liquid Solder ◽  
Area Array ◽  
Cost Effective Method ◽  
Passive Alignment

AbstractPassive alignment techniques using area array solder joints are currently under investigation as a cost effective method of achieving electro-optical interconnects in electronic packages. Several investigators have developed models that describe the shapes of and forces produced by the liquid solder drops during reflow. These models are reviewed to provide a scientific basis for the application of such techniques.

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