Discussion on the Reliability Issues of Solder-Bump and Direct-Solder Bonded Power Device Packages Having Double-Sided Cooling Capability

2005 ◽  
Vol 128 (3) ◽  
pp. 208-214 ◽  
Author(s):  
John G. Bai ◽  
Jesus N. Calata ◽  
Guo-Quan Lu
Keyword(s):  
Thermal Cycling ◽  
Solder Bump ◽  
Coefficient Of Thermal Expansion ◽  
Operating Temperature ◽  
Power Device ◽  
Element Analysis ◽  
Temperature Changes ◽  
Power Cycling ◽  
Thermomechanical Reliability ◽  
Cycling Experiment

Power device packages with solder-bump (SB) and direct-solder (DS) interconnections were fabricated and some of their thermomechanical reliability issues were discussed based on both thermal cycling experiment and finite element analysis (FEA). The SB interconnection shows superior reliability over the DS interconnection in the thermal cycling experiment because the mismatched coefficient of thermal expansion leads to smaller stresses at the SB interconnection under the same temperature changes. On the other hand, FEA results show that the DS package has significantly lower operating temperatures under the same double-sided cooling condition. After considering the operating temperature difference, the DS package was shown to be superior over the SB package in the power cycling analysis.

Analysis of Thermal Displacements Due to CTE Mismatches Using FEA Simulation and Experimental Validation With a Differential Variable Reluctance Transducer

2007 ◽  
Author(s):  
Tony A. Asghari ◽  
Joseph Janas
Keyword(s):  
Thermal Loading ◽  
Coefficient Of Thermal Expansion ◽  
Relative Displacement ◽  
Linear Displacement ◽  
System Level ◽  
Element Analysis ◽  
Variable Reluctance ◽  
Power Cycling ◽  
Thermal Displacements ◽  
Fea Simulation

Deformation induced by thermal loading in a severe automotive environment, between an electronic ceramic substrate — bonded to an aluminum heatsink — and an adjacent nylon material, was investigated by numerical and experimental methods. The goal of this paper is to quantify the relative displacement of certain points of interest, where an aluminum wire bond exists. This displacement is caused by 1) coefficient of thermal expansion (CTE) mismatches of various parts of the assembly when temperature distribution is uniform, and 2) when temperature gradients exist in either steady-state or transient conditions due to thermal cycling (between +150°C and −40°C) as well as power cycling. ANSYS Workbench™ finite element analysis (FEA) software was used to model the system level deformation under various conditions. A unique, quick, and repeatable method of experimentally measuring displacement using a Differential Variable Reluctance Transducer (DVRT®) was utilized. The DVRT® and its signal conditioner provide an analog DC voltage output, which is proportional to linear displacement (resolution as fine as 1.5 micrometer). Error inherent to the DVRT® was adjusted by further testing using a modified sample of Invar. The numerical and experimental results showed good overall correlation.

Thermomechanical Stress and Warpage Augmentation Using Auxetic Features in Electronic Design

2019 ◽  
Author(s):  
Mahsa Montazeri ◽  
John Harris ◽  
David R. Huitink ◽  
Adithya Venkatanarayanan ◽  
Simon S. Ang
Keyword(s):  
Thermal Cycling ◽  
Stress Reduction ◽  
Coefficient Of Thermal Expansion ◽  
Ground Plane ◽  
Tensile Load ◽  
Maximum Temperature ◽  
Electronic Packages ◽  
Element Analysis ◽  
Interfacial Stresses ◽  
Auxetic Structures

Abstract One of the leading contributors to assembly and reliability issues in electronic packaging arises from warpage and interfacial stresses stemming from coefficient of thermal expansion (CTE) mismatch of the interfacing components. Trends toward miniaturizing and increasing density of the electronic packages exacerbate the assembly problems, leading to issues such as die cracking and board level assembly yield loss. One potential solution may be found in the inclusion of auxetic structures, which demonstrate negative Poisson’s ratio through re-entrant geometries, which has been investigated for use in augmented structural mechanics for impact energy absorption. Because of the unique structural design, auxetics become thicker perpendicularly under an applied tensile load, unlike typical material loading responses. This interesting behavior has opportunity for integration into electronic packages for stress mitigation under thermal cycling since the structures can disrupt the typical expansion behavior. Here, auxetic trace geometries and structures were evaluated in various packaging implementations (die and substrate level) for warpage and stress reduction under thermal cycling conditions. By replacing standard Manhattan-style layouts and power and ground plane features with re-entrant trace geometries, reductions in thermomechanically induced interfacial stresses were observed, in addition to considering heat spreading properties within a package. Herein, deformation of silicon chip with addition of raised re-entrant Evans auxetics and raised ellipse shape auxetic traces as well as deformation of direct bonded copper (DBC) substrate with and without re-entrant auxetic patterned pads are estimated and compared using Finite Element Analysis (FEA) in ANSYS software. To demonstrate the benefits of passive auxetic traces, a planar transformer with re-entrant Evans auxetic patterns on PCB layers has been examined under full-load operating condition and compared with a traditionally patterned transformers. A better thermal distribution and lower maximum temperature in the device are achieved by including auxetic patterned features. FEA simulation results also show stress reduction in windings and lower deformation in PCB layers. Inclusion of auxetic structures in passive metal deposition layers which are not part of the circuit is shown to reduce maximum stress and warp deflection, as well as improve thermal gradient distribution and reduce overall temperature for 2D planar and 3D stacked packages. Consequently, use of auxetic features may extend package reliability significantly.

Interconnect Fatigue Failure Parameter Isolation for Power Device Reliability Prediction in Alternative Accelerated Mechanical Cycling Test

2019 ◽  
Vol 141 (3) ◽  
Author(s):  
Mahsa Montazeri ◽  
Cody J. Marbut ◽  
David Huitink
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Mechanical Stresses ◽  
Power Device ◽  
Reliability Test ◽  
Test Duration ◽  
Force Frequency ◽  
Solder Interconnects ◽  
Mechanical Cycling ◽  
Power Cycling

In this work, a rapid and low-cost accelerated reliability test methodology which was designed to simulate mechanical stresses induced in flip–chip bonded devices during the thermal cycling reliability test under isothermal conditions, is introduced and demonstrated using power device analogous test chips. By stressing these devices in a controlled environment, mechanical stresses become decoupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device relevant, flip–chip solder interconnects while monitoring for failure. Herein, finite element analysis (FEA) is used to extract various damage metrics of different solder materials, including PbSn37/63, SAC305, and nanosilver, in both thermal operation and the introduced alternative mechanical testing conditions. Plastic work density and strain are calculated in the critical solder interconnects as factors that indicate the amount of the damage accumulation per cycle during the mechanical cycling, thermal cycling, and power cycling tests. The number of cycles to failure for each test was calculated using the fatigue life model developed by Darveaux for eutectic PbSn solder, while for SAC305 Syed's method was used, and for nanosilver, the Knoerr et al. equations are applied. The effects of environmental temperature and shearing force frequency were studied for the mechanical cycling reliability test, where a modified Norris–Landzberg equation for mechanical cycling tests was explored using the simulation results. Finally, comparing the mechanical cycling with the equivalent thermal cycling and power cycling demonstrated a significant reduction in required test duration to achieve a reliability estimation.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Heat Transfer and Thermal Stress Analysis of an Optoelectronic Package

1991 ◽  
Vol 113 (3) ◽  
pp. 258-262 ◽  
Author(s):  
J. G. Stack ◽  
M. S. Acarlar
Keyword(s):  
Heat Transfer ◽  
Thermal Management ◽  
Power Dissipation ◽  
Point Of View ◽  
Optical Data ◽  
Data Link ◽  
Element Analysis ◽  
Thermally Induced ◽  
Temperature Changes ◽  
Induced Stresses

The reliability and life of an Optical Data Link transmitter are inversely related to the temperature of the LED. It is therefore critical to have efficient packaging from the point of view of thermal management. For the ODL® 200H devices, it is also necessary to ensure that all package seals remain hermetic throughout the stringent military temperature range requirements of −65 to +150°C. For these devices, finite element analysis was used to study both the thermal paths due to LED power dissipation and the thermally induced stresses in the hermetic joints due to ambient temperature changes

Analysis of Long-Term and Thermal Cycling Tests for a Commercial Solid Oxide Fuel Cell

2017 ◽  
Vol 14 (4) ◽  
Author(s):  
Dustin Lee ◽  
Jing-Kai Lin ◽  
Chun-Huang Tsai ◽  
Szu-Han Wu ◽  
Yung-Neng Cheng ◽  
...  
Keyword(s):  
Fuel Cell ◽  
Thermal Cycling ◽  
Solid Oxide Fuel Cell ◽  
Coefficient Of Thermal Expansion ◽  
Solid Oxide ◽  
Oxide Fuel ◽  
Flow Rates ◽  
Degradation Rates ◽  
Two Stages

The effects of isothermally long-term and thermal cycling tests on the performance of an ASC type commercial solid oxide fuel cell (SOFC) have been investigated. For the long-term test, the cells were tested over 5000 h in two stages, the first 3000 h and the followed 2000 h, under the different flow rates of hydrogen and air. Regarding the thermal cycling test, 60 cycles in total were also divided into two sections, the temperature ranges of 700 °C to 250 °C and 700 °C to 50 °C were applied for the every single cycle of first 30 cycles and the later 30 cycles, respectively. The results of long-term test show that the average degradation rates for the cell in the first 3000 h and the followed 2000 h under different flow rates of fuel and air are 1.16 and 2.64%/kh, respectively. However, there is only a degradation of 6.6% in voltage for the cell after 60 thermal cycling tests. In addition, it is found that many pores formed in the anode of the cell which caused by the agglomeration of Ni after long-term test. In contrast, the vertical cracks penetrating through the cathode of the cell and the in-plane cracks between the cathode and barrier layer of the cell formed due to the coefficient of thermal expansion (CTE) mismatch after 60 thermal cycling tests.

A Highly Accelerated Thermal Cycling (HATC) Test for Solder Reliability Assessment in BGA Packages

2007 ◽  
Author(s):  
X. Long ◽  
I. Dutta ◽  
R. Guduru ◽  
R. Prasanna ◽  
M. Pacheco
Keyword(s):  
Thermal Cycling ◽  
Solder Joints ◽  
Low Cycle Fatigue ◽  
Inelastic Strain ◽  
Fatigue Reliability ◽  
Element Analysis ◽  
Mechanical Cycling ◽  
Experimental Apparatus ◽  
Dependent Strain ◽  
Accelerated Thermal Cycling

A thermo-mechanical loading system, which can superimpose a temperature and location dependent strain on solder joints, is proposed in order to conduct highly accelerated thermal-mechanical cycling (HATC) tests to assess thermal fatigue reliability of Ball Grid Array (BGA) solder joints in microelectronics packages. The application of this temperature and position dependent strain produces generally similar loading modes (shear and tension) encountered by BGA solder joints during service, but substantially enhances the inelastic strain accumulated during thermal cycling over the same temperature range as conventional ATC (accelerated thermal cycling) tests, thereby leading to a substantial acceleration of low-cycle fatigue damage. Finite element analysis was conducted to aid the design of experimental apparatus and to predict the fatigue life of solder joints in HATC testing. Detailed analysis of the loading locations required to produce failure at the appropriate joint (next to the die-edge ball) under the appropriate tension/shear stress partition are presented. The simulations showed that the proposed HATC test constitutes a valid methodology for further accelerating conventional ATC tests. An experimental apparatus, capable of applying the requisite loads to a BGA package was constructed, and experiments were conducted under both HATC and ATC conditions. It is shown that HATC proffers much reduced cycling times compared to ATC.

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