Interconnect Fatigue Failure Parameter Isolation for Power Device Reliability Prediction in Alternative Accelerated Mechanical Cycling Test

2019 ◽  
Vol 141 (3) ◽  
Author(s):  
Mahsa Montazeri ◽  
Cody J. Marbut ◽  
David Huitink
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Mechanical Stresses ◽  
Power Device ◽  
Reliability Test ◽  
Test Duration ◽  
Force Frequency ◽  
Solder Interconnects ◽  
Mechanical Cycling ◽  
Power Cycling

In this work, a rapid and low-cost accelerated reliability test methodology which was designed to simulate mechanical stresses induced in flip–chip bonded devices during the thermal cycling reliability test under isothermal conditions, is introduced and demonstrated using power device analogous test chips. By stressing these devices in a controlled environment, mechanical stresses become decoupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device relevant, flip–chip solder interconnects while monitoring for failure. Herein, finite element analysis (FEA) is used to extract various damage metrics of different solder materials, including PbSn37/63, SAC305, and nanosilver, in both thermal operation and the introduced alternative mechanical testing conditions. Plastic work density and strain are calculated in the critical solder interconnects as factors that indicate the amount of the damage accumulation per cycle during the mechanical cycling, thermal cycling, and power cycling tests. The number of cycles to failure for each test was calculated using the fatigue life model developed by Darveaux for eutectic PbSn solder, while for SAC305 Syed's method was used, and for nanosilver, the Knoerr et al. equations are applied. The effects of environmental temperature and shearing force frequency were studied for the mechanical cycling reliability test, where a modified Norris–Landzberg equation for mechanical cycling tests was explored using the simulation results. Finally, comparing the mechanical cycling with the equivalent thermal cycling and power cycling demonstrated a significant reduction in required test duration to achieve a reliability estimation.

Discussion on the Reliability Issues of Solder-Bump and Direct-Solder Bonded Power Device Packages Having Double-Sided Cooling Capability

2005 ◽  
Vol 128 (3) ◽  
pp. 208-214 ◽  
Author(s):  
John G. Bai ◽  
Jesus N. Calata ◽  
Guo-Quan Lu
Keyword(s):  
Thermal Cycling ◽  
Solder Bump ◽  
Coefficient Of Thermal Expansion ◽  
Operating Temperature ◽  
Power Device ◽  
Element Analysis ◽  
Temperature Changes ◽  
Power Cycling ◽  
Thermomechanical Reliability ◽  
Cycling Experiment

Power device packages with solder-bump (SB) and direct-solder (DS) interconnections were fabricated and some of their thermomechanical reliability issues were discussed based on both thermal cycling experiment and finite element analysis (FEA). The SB interconnection shows superior reliability over the DS interconnection in the thermal cycling experiment because the mismatched coefficient of thermal expansion leads to smaller stresses at the SB interconnection under the same temperature changes. On the other hand, FEA results show that the DS package has significantly lower operating temperatures under the same double-sided cooling condition. After considering the operating temperature difference, the DS package was shown to be superior over the SB package in the power cycling analysis.

Characterization of Die Stress Distributions in Area Array Flip Chip Packaging

2009 ◽  
Author(s):  
Jordan Roberts ◽  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Power ◽  
Temperature Cycling ◽  
Aging Effects ◽  
Area Array ◽  
Power Cycling ◽  
Die Stress ◽  
On Chip ◽  
Test Chips

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during thermal cycling and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach also allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, initial experiments have been performed to analyze the effects of thermal cycling and power cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). Power cycling of selected parts was performed by exciting the on-chip heaters on the test chips with power levels typical of microprocessor die. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show some cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of temperature cycling duration are currently being correlated with the delaminations occurring at the interfaces between the die and underfill and the die and lid adhesive. In addition, finite element models of the packages are being developed and correlated with the data.

Shorter Field Life in Power Cycling for Organic Packages

2006 ◽  
Vol 129 (1) ◽  
pp. 28-34 ◽  
Author(s):  
S. B. Park ◽  
Izhar Z. Ahmed
Keyword(s):  
Fatigue Life ◽  
Temperature Distribution ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Uniform Temperature ◽  
Transfer Coefficients ◽  
Solder Interconnects ◽  
Power Cycling ◽  
Plastic Ball ◽  
Accelerated Thermal Cycling

The importance of power cycling as a mean of reliability assessment was revisited for flip chip plastic ball grid array (FC-PBGA) packages. Conventionally, reliability was addressed empirically through accelerated thermal cycling (ATC) because of its simplicity and conservative nature of life prediction. It was well accepted and served its role effectively for ceramic packages. In reality, an assembly is subjected to a power cycling, i.e., nonuniform temperature distribution with a chip as the only heat source and other components as heat dissipaters. This non-uniform temperature distribution and different coefficient of thermal expansion (CTE) of each component make the package deform differently than the case of uniform temperature in ATC. Higher substrate CTE in a plastic package generates double curvature in the package deformation and transfers higher stresses to the solder interconnects at the end of die. This mechanism makes the solder interconnects near the end of die edge fail earlier than those of the highest distance to neutral point. This phenomenon makes the interconnect fail earlier in power cycling than ATC. Apparently, we do not see this effect (the die shadow effect) in ceramic packages. In this work, a proper power cycling analysis procedure was proposed and conducted to predict solder fatigue life. An effort was made for FC-PBGA to show the possibility of shorter fatigue life in power cycling than the one of ATC. The procedure involves computational fluid dynamics (CFD) and finite element analyses (FEA). CFD analysis was used to extract transient heat transfer coefficients while subsequent FEA–thermal and FEA–structural analyses were used to calculate temperature distribution and strain energy density, respectively.

Strategies for Improving Reliability of Solder Joints on Power Semiconductor Devices

2003 ◽  
Author(s):  
Guo-Quan Lu ◽  
Xingsheng Liu ◽  
Sihua Wen ◽  
Jesus Noel Calata ◽  
John G. Bai
Keyword(s):  
Finite Element ◽  
Solder Joint ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Solder Joints ◽  
Mechanical Stresses ◽  
Flexible Substrates ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Reliability Of Solder Joints

There has been a significant research effort on area-array flip-chip solder joint technology in order to reduce package footprint, enhance current handling capability, and improve heat dissipation. However, there is a lingering concern over cyclic fatigue of solder alloys by thermo-mechanical stresses arising from mismatched thermal expansion coefficients of expansion among the various components of the package. In this paper, some strategies taken to improve the reliability of solder joints on power devices in single-device and multi-chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple-stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint while the underfill provides a load transfer from the joints. Flexible substrates can deform to relieve thermo-mechanical stresses. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing, and finite-element analyses of an interconnection structure, termed the Dimple-Array Interconnect (DAI), for improving the solder joint reliability is also presented. In the DAI structure, a solder is used to join arrays of dimples pre-formed on a metal sheet onto the bonding pads of a device. Finite-element thermo-mechanical analyses and thermal cycling data show that the dimple-array solder joints are more fatigue-resistant than the conventional barrel-shaped solder joints in flip-chip IC packages.

Interconnect Fatigue Failure Parameter Isolation for Power Device Reliability Prediction

2018 ◽  
Author(s):  
Cody J. Marbut ◽  
Mahsa Montazeri ◽  
David Huitink
Keyword(s):  
Shear Stress ◽  
Mechanical Testing ◽  
Flip Chip ◽  
Mechanical Stresses ◽  
Operating Conditions ◽  
Stress Factors ◽  
Reliability Prediction ◽  
Power Devices ◽  
Test Protocol ◽  
Solder Interconnects

Flip chip (FC) packaging techniques in modern power electronics have enabled increased power density in module performance, but mechanical stresses induced by thermal expansion during inherent operating conditions in the power devices and packages create a need for understanding thermomechanical fatigue mechanisms that lead to reliability concerns. Moreover, in actual use, these mechanical stresses impact the reliable lifetime alongside thermal factors (such as diffusion and microstructural transformation) and other process history effects. This amalgam of damage inducing phenomena make development of a concise association between damage, fatigue, and stress factors difficult to determine. For reliability demonstration under fatigue loading, accelerated life testing (ALT), such as Thermal Cycling (TC), are commonly used in industry; however, long duration and expensive equipment required for TC limit its utility, especially when considering the high cost of wide-bandgap devices and modules, and the limitation of high temperature (> 150°C) testing standards. As a result, alternative test methodologies are needed to provide faster, cheaper, and design integrable reliability determination. In this work, an accelerated test methodology is introduced and designed to simulate these mechanical stresses at isothermal conditions, which is demonstrated using test chips that are analogous to power devices. By stressing these devices in a controlled environment, mechanical stresses become de-coupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device-relevant, flip-chip solder interconnects while monitoring cycles-to-failure (CTF). Also, Finite Element Analysis (FEA) is used to extract various damage metrics of different solder materials (including PbSn37/63, SAC305 and Nano-silver) in both thermal operation and the introduced alternative mechanical testing conditions. In doing so, test protocol translations to common qualification tests (or use condition thermal profiles) can be determined and are validated using the mechanical shear stress testing method. Plastic work density and maximum shear were calculated in the critical solder interconnects for different isothermal mechanical testing temperatures (22°C, 75°C, 100°C and 125°C) and the results are compared with the simulation results of different TC test conditions. This reliability determination with failure parameter isolation allows for improved integration with FEA modeling for a priori reliability prediction during the design process.

Measurement of Microprocessor Die Stress due to Thermal Cycling, Power Cycling, and Second Level Assembly

2013 ◽  
Author(s):  
Jordan C. Roberts ◽  
Mohammad Motalab ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Power ◽  
Three Dimensional ◽  
Power Cycling ◽  
Die Stress ◽  
Test Chips ◽  
Resistance Data ◽  
Critical Locations

In the current work, we have extended our past studies on Flip Chip Ceramic Ball Grid Array (FC-BGA) microprocessor packaging configurations to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings. Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time.

Development of a Novel Test Setup to Study the Combined Effects of Electromigration and Mechanical Stress in Solder Interconnects

2020 ◽  
Author(s):  
Mahsa Montazeri ◽  
David R. Huitink
Keyword(s):  
Tensile Stress ◽  
Thermal Cycling ◽  
Current Density ◽  
Flip Chip ◽  
High Current Density ◽  
Operating Conditions ◽  
Reliability Estimation ◽  
High Current ◽  
Test Setup ◽  
Solder Interconnects

Abstract One key concern that arises from scaling of device interconnects with increasing power density requirements is electromigration (EM). On the other hand, thermal cycling fatigue has always been a reliability challenge in solder interconnects. Variations in device temperature caused by environmental or operating conditions induce stress in solders, as they usually connect two components with different coefficients of thermal expansion (CTE). These thermally induced stresses may lead to crack formation within the solders. The combination of EM effects and thermal cycling add to the complexity of the reliability estimation for high current density applications. In this work, a novel test setup has been designed and developed to estimate the reliability of solder interconnects under high current density, while a constant tensile stress is also applied to the solder interconnect. The test set up offers the ability to test up to four samples at the same time. Additionally, the test samples are fabricated with two copper wires connected by Pb/Sn solder to imitate copper UBM in a flip-chip bonding connection. Strain in solder is measured by monitoring the elongation of the wire during testing, while failure of the connection is detected by continuous monitoring of the electrical resistance. The experiment is conducted for conditions including pure tensile stress, pure EM and coupled EM and tensile stress where a significant reduction in life-time is observed for the coupled degradation effects. Comparing the experimental results of different current densities at different stress levels will help in identifying the nature of degradation in solders, which will help inform the drive for miniaturization.

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