A 180 nm copper/low-k CMOS technology with dual gate oxide optimized for low power and low cost consumer wireless applications

2002 ◽  
Author(s):  
G.C.-F. Yeap ◽  
F. Nkansah ◽  
J. Chen ◽  
S. Jallepalli ◽  
D. Pham ◽  
...  
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Wireless Applications ◽  
Dual Gate ◽  
Low K

Deep Submicron CMOS Technology Using Top-Edge Round STI and Dual Gate Oxide for Low Power 256 M-Bit Mobile DRAM

2003 ◽  
Vol 42 (Part 1, No. 4B) ◽  
pp. 1892-1896 ◽  
Author(s):  
Chihoon Lee ◽  
Donggun Park ◽  
Namhyuk Jo ◽  
Chanseong Hwang ◽  
Hyeong Joon Kim ◽  
...  
Keyword(s):  
Low Power ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Dual Gate ◽  
Submicron Cmos

scholarly journals Ambient Backscatterers Using FM Broadcasting for Low Cost and Low Power Wireless Applications

2017 ◽  
Vol 65 (12) ◽  
pp. 5251-5262 ◽  
Author(s):  
Spyridon Nektarios Daskalakis ◽  
John Kimionis ◽  
Ana Collado ◽  
George Goussetis ◽  
Manos M. Tentzeris ◽  
...  
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Wireless Applications

AN EFFICIENT LOW-POWER SIGMA-DELTA MODULATOR FOR MULTI-STANDARD WIRELESS APPLICATIONS

2012 ◽  
Vol 21 (04) ◽  
pp. 1250028 ◽  
Author(s):  
B. HODA SEYEDHOSSEINZADEH ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Cmos Technology ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Wireless Applications ◽  
Design And Implementation ◽  
Simulation Results ◽  
System Level Simulations

This paper describes the design and implementation of a reconfigurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital reconfigurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulations as well as transistor-level simulations of the modulator. HSPICE simulation results show that the proposed modulator achieves 76.8/78.9/80.8/85/89.5 dB peak signal-to-noise plus distortion ratio (SNDR) within the standards WiFi, WiMAX, WCDMA, Bluetooth and GSM with the bandwidth of 12.5 MHz, 10 MHz, 1.92 MHz, 0.5 MHz, and 250 kHz, respectively, under the power consumption of 37/37/12/5/5 mW using a single 1 V power supply.

scholarly journals Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-13 ◽  
Author(s):  
Jianhong Xiao ◽  
Guang Zhang ◽  
Tianwei Li ◽  
Jose Silva-Martinez
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Building Blocks ◽  
Cmos Technology ◽  
Digital Television ◽  
Main Stream ◽  
Image Rejection ◽  
Fully Integrated ◽  
Front End ◽  
Image Rejection Ratio

A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

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