2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

Copper distribution behavior near a SiO/sub 2//Si interface by low-temperature (>400°C) annealing and its influence on electrical characteristics of MOS-capacitors

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852754 ◽

2002 ◽

Cited By ~ 2

Author(s):

K. Hozawa ◽

T. Itoga ◽

S. Isomae ◽

J. Yugami ◽

M. Ohkura

Keyword(s):

Low Temperature ◽

Electrical Characteristics ◽

Mos Capacitors ◽

Copper Distribution ◽

Distribution Behavior

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Breakdown measurements of ultra-thin SiO/sub 2/ at low voltage

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852783 ◽

2002 ◽

Cited By ~ 10

Author(s):

J.H. Stathis ◽

A. Vayshenker ◽

P.R. Varekamp ◽

E.Y. Wu ◽

C. Montrose ◽

...

Keyword(s):

Low Voltage

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A novel 1T1C capacitor structure for high density FRAM

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852758 ◽

2002 ◽

Cited By ~ 6

Author(s):

N.W. Jang ◽

Y.J. Song ◽

H.H. Kim ◽

D.J. Jung ◽

B.J. Koo ◽

...

Keyword(s):

High Density ◽

Capacitor Structure

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0.18 um modular triple self-aligned embedded split-gate flash memory

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852793 ◽

2002 ◽

Cited By ~ 7

Author(s):

R. Mih ◽

J. Harrington ◽

K. Houlihan ◽

Hyun Koo Lee ◽

K. Chan ◽

...

Keyword(s):

Flash Memory

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EB projection lithography for 60-80 nm ULSI fabrication

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852767 ◽

2002 ◽

Cited By ~ 1

Author(s):

K. Tokunaga ◽

F. Koba ◽

M. Miyasaka ◽

Y. Takaishi ◽

K. Noda ◽

...

Keyword(s):

Projection Lithography ◽

Ulsi Fabrication

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Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852826 ◽

2002 ◽

Cited By ~ 9

Author(s):

K. Mistry ◽

T. Ghani ◽

M. Armstrong ◽

S. Tyagi ◽

P. Packan ◽

...

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A conformal ruthenium electrode for MIM capacitors in Gbit DRAMs using the CVD technology based on oxygen-controlled surface reaction

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852786 ◽

2002 ◽

Cited By ~ 4

Author(s):

M. Hiratani ◽

T. Nabatame ◽

Y. Matsui ◽

Y. Shimamoto ◽

Y. Sasago ◽

...

Keyword(s):

Surface Reaction ◽

Mim Capacitors

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A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852818 ◽

2002 ◽

Cited By ~ 7

Author(s):

P. Smeys ◽

V. McGahay ◽

I. Yang ◽

J. Adkisson ◽

K. Beyer ◽

...

Keyword(s):

High Performance ◽

Cmos Technology ◽

Cu Interconnects ◽

Low K ◽

Soi Cmos

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Auger recombination enhanced hot carrier degradation in nMOSFETs with positive substrate bias

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852798 ◽

2002 ◽

Cited By ~ 4

Author(s):

L.P. Chiang ◽

C.W. Tsai ◽

T. Wang ◽

U.C. Liu ◽

M.C. Wang ◽

...

Keyword(s):

Auger Recombination ◽

Substrate Bias ◽

Hot Carrier ◽

Hot Carrier Degradation

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A new cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852788 ◽

2002 ◽

Author(s):

H. Itoh ◽

Y. Tsunemine ◽

A. Yutani ◽

T. Okudaira ◽

K. Kashihara ◽

...

Keyword(s):

Alloy Coating ◽

Cell Technology

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Copper distribution behavior near a SiO/sub 2//Si interface by low-temperature (>400°C) annealing and its influence on electrical characteristics of MOS-capacitors

Breakdown measurements of ultra-thin SiO/sub 2/ at low voltage

A novel 1T1C capacitor structure for high density FRAM

0.18 um modular triple self-aligned embedded split-gate flash memory

EB projection lithography for 60-80 nm ULSI fabrication

Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices

A conformal ruthenium electrode for MIM capacitors in Gbit DRAMs using the CVD technology based on oxygen-controlled surface reaction

A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

Auger recombination enhanced hot carrier degradation in nMOSFETs with positive substrate bias

A new cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Copper distribution behavior near a SiO/sub 2//Si interface by low-temperature (>400°C) annealing and its influence on electrical characteristics of MOS-capacitors

Breakdown measurements of ultra-thin SiO/sub 2/ at low voltage

A novel 1T1C capacitor structure for high density FRAM

0.18 um modular triple self-aligned embedded split-gate flash memory

EB projection lithography for 60-80 nm ULSI fabrication

Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices

A conformal ruthenium electrode for MIM capacitors in Gbit DRAMs using the CVD technology based on oxygen-controlled surface reaction

A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

Auger recombination enhanced hot carrier degradation in nMOSFETs with positive substrate bias

A new cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)
Latest Publications